CY28446
Byte 1: Control Register 1
Bit
@Pup
Name
Description
0
0
CPU PLL Spread Enable PLL1 (CPU PLL) Spread Spectrum Enable
0 = Spread off
1 = Spread on (–0.5% spread spectrum on CPU/SRC/PCI clocks)
Byte 2: Control Register 2
Bit
7
@Pup
Name
Reserved
Reserved
PCI3
Description
1
1
1
Reserved set to 1
Reserved set to 1
6
5
PCI3 Output Enable
0 = Disable, 1 = Enable
4
3
2
1
1
1
PCI2
PCI1
PCI0
PCI2 Output Enable
0 = Disable, 1 = Enable
PCI1Output Enable
0 = Disable, 1 = Enable
PCI0 Output Enable
0 = Disable, 1 = Enable
1
0
1
1
Reserved
Reserved
Reserved set to 1
Reserved set to 1
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
0
SRC7
Allow control of SRC[T/C]7 with assertion of OEB#
0 = Free running, 1 = Stopped with OEB#
6
5
0
0
Reserved
SRC5
Reserved set to 0
Allow control of SRC[T/C]5 with assertion of OEB#
0 = Free running, 1 = Stopped with OEB#
4
3
2
0
0
0
Reserved
Reserved
SRC2
Reserved set to 0
Reserved set to 0
Allow control of SRC[T/C]2 with assertion of OEB#
0 = Free running, 1 = Stopped with OEB#
1
0
0
0
Reserved
Reserved
Reserved set to 0
Reserved set to 0
Byte 4: Control Register 4
Bit
7
@Pup
Name
Description
1
0
Reserved
DOT96[T/C]
Reserved set to 1
6
DOT PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
5
4
3
0
1
0
Reserved
Reserved
PCIF0
Reserved set to 0
Reserved set to 1
Allow control of PCIF0 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2
1
0
1
1
1
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
Allow control of CPU[T/C]2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Rev 1.0,November 20, 2006
Page 6 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
