CY28446
Byte 5: Control Register 5
Bit
7
@Pup
Name
Description
0
0
Reserved
CPU[T/C]2
Reserved set to 0
6
CPU[T/C]2 Stop Drive Mode
0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP#
asserted
5
4
0
0
CPU[T/C]1
CPU[T/C]0
CPU[T/C]1 Stop Drive Mode
0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP#
asserted
CPU[T/C]0 Stop Drive Mode
0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP#
asserted
3
2
1
0
0
0
0
0
SRC[T/C]
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
SRC[T/C] PWRDWN Drive Mode
0 = Driven when PD asserted, 1 = Tri-state when PD asserted
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted, 1 = Tri-state when PD asserted
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted, 1 = Tri-state when PD asserted
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted, 1 = Tri-state when PD asserted
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
0
REF/N or Tri-state Select REF/N or Tri-state Select
1 = REF/N, 0 = Tri-state
6
0
Test Mode
Test Mode Control
1 = Ref/N or Tristate, 0 = Normal Operation
5
4
1
0
Reserved
REF
Reserved set to 1
REF Output Drive Strength
0 = Low, 1 = High
3
1
PCI and PCIF clock SW PCI_STP Function
outputs except those set 0 = SW PCI_STP assert, 1 = SW PCI_STP deassert
to free running
When this bit is set to 0, all STOPPABLE PCI and PCIF outputs are
stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI and PCIF outputs resumes in
a synchronous manner with no short pulses.
2
1
0
HW
HW
HW
FS_C
FS_B
FS_A
FSC Reflects the value of the FS_C pin sampled on power-up
0 = FSC was low during VTT_PWRGD# assertion
FSB Reflects the value of the FS_B pin sampled on power-up
0 = FSB was low during VTT_PWRGD# assertion
FSA Reflects the value of the FS_A pin sampled on power-up
0 = FSA was low during VTT_PWRGD# assertion
Byte 7: Vendor ID
Bit
7
@Pup
Name
Description
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
0
0
1
1
1
0
0
0
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
6
5
4
3
2
Vendor ID Bit 2
Vendor ID Bit 2
1
Vendor ID Bit 1
Vendor ID Bit 1
0
Vendor ID Bit 0
Vendor ID Bit 0
Rev 1.0,November 20, 2006
Page 7 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
