CY28446
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
8:2
9
Slave address–7 bits
Write
8:2
9
Slave address–7 bits
Write
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeated start
18:11
19
18:11
19
27:20
28
20
Acknowledge from slave
Stop
27:21
28
Slave address–7 bits
Read
29
29
Acknowledge from slave
Data from slave–8 bits
NOT Acknowledge
Stop
37:30
38
39
Control Registers
Byte 0: Control Register 0
Bit
@Pup
Name
Description
7
1
CPU2_ITP[T/C]/SRC7[T/C] CPU2_ITP[T/C]/SRC[T/C]7 Output Enable
0 = Disable (Tri-state), 1 = Enable
6
5
1
1
SRC[T/C]6
SRC[T/C]6 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]5
SRC[T/C]5 Output Enable
0 = Disable (Tri-state), 1 = Enable
4
3
1
1
Reserved
Reserved
SRC[T/C]3
SRC[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
2
1
0
1
1
1
SRC[T/C]2
SRC[T/C]1
SRC[T/C]0
SRC[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enable
Byte 1: Control Register 1
Bit
@Pup
Name
Description
7
1
PCIF0
PCIF0 Output Enable
0 = Disable, 1 = Enable
6
5
4
1
1
1
DOT_96[T/C]
USB_48
REF
DOT_96 MHz Output Enable
0 = Disable (Tri-state), 1 = Enable
USB_48 Output Enable
0 = Disable, 1 = Enable
REF Output Enable
0 = Disable, 1 = Enable
3
2
1
1
Reserved
Reserved
CPU[T/C]1
CPU[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
1
1
CPU[T/C]0
CPU[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enable
Rev 1.0,November 20, 2006
Page 5 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
