CY28446
Pin Description
Pin No.
Name
VSS_48
Type
Description
1
GND Ground for outputs.
2, 3, 5, 6, 8, SRC(0:3, 5:6, 8:10) O, DIF 100 MHz Differential serial reference clocks
9, 13, 14, 18, [T/C]
19, 20, 21,
22, 23, 25,
26, 27, 28
4, 7, 12, 15, OE[0, 1, 3, 6, A, B]#
24, 64
I, PU 3.3V LVTTL input for enabling assigned SRC clock (active LOW)
10, 17, 29,
11, 30, 33
16
VDD_SRC
VSS_SRC
PCI_STP#
PWR 3.3V power supply for outputs.
GND Ground for outputs.
I, PU 3.3V LVTTL input for PCI_STP#
Stops SRC and PCI clocks not set to free running in the SMBUS registers.
31, 32
CPU2_ITPT/SRCT7, O, DIF Selectable differential CPU clock/100 MHz Differential serial reference clock.
CPU2_ITPC/SRCC7
Selectable via Pin 53 PCIF0/ITP_EN
O, DIF Differential CPU clock outputs.
PWR 3.3V power supply for outputs.
GND Ground for outputs.
34, 35, 38, 39 CPUT/C[0:1]
36
37
40
41
42
VDD_CPU
VSS_CPU
CPU_STP#
SCLK
I, PU 3.3V LVTTL input for CPU_STP# active LOW.
I
SMBus-compatible SCLOCK.
SDATA
I/O, SMBus-compatible SDATA.
OD
43
VDD_REF
XOUT
PWR 3.3V power supply for outputs.
O, SE 14.318 MHz crystal output.
44
45
XIN
I
14.318 MHz crystal input.
46
VSS_REF
REF
GND Ground for outputs.
47
O,SE Fixed 14.318 MHz clock output.
PWR 3.3V power supply for outputs.
O, SE 33 MHz clock output
48, 54
VDD_PCI
49, 50, 51, 52 PCI[0:3]
53
PCIF0/ITP_EN
I/O, PD 33 MHz clock output (not stoppable by PCI_STOP#)/3.3V LVTTL input for
selecting pins 31/32 (CPU2_ITP[T/C]/SRC7[T/C]) (sampled on the
VTT_PWRGD# assertion).
0 (default): SRC7[T/C]
1: CPU2_ITP[T/C]
55, 59
56
VSS_PCI
GND Ground for outputs.
VTT_PWRGD#/PD
I, PD 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,
FS_C, and all I/O configuration pins,. After VTT_PWRGD# (active LOW) assertion,
this pin becomes a real-time input for asserting power-down (active HIGH).
57
58
FS_C/TEST_SEL
USB_48/FS_A
I, PD 3.3V-tolerant input for CPU frequency selection/Selects test mode if pulled to
IMFS_C when VTT_PWRGD# is asserted LOW.
V
Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifica-
tions.
I/O, PU Fixed 48 MHz clock output/3.3V-tolerant input for CPU frequency selection.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
60
VDD_48
PWR 3.3V power supply for outputs.
O, DIF Fixed 96 MHz clock output.
61,62
63
DOT_96[T/C]
FS_B/TEST_MODE
I, PU 3.3V-tolerant input for CPU frequency selection Selects Ref/N or Tri-state
when in test mode
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Rev 1.0,November 20, 2006
Page 3 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
