CY28346-2
CPU_STP# Clarification
(Mult 0 ‘select’) x (Iref), and the CPUC signal will not be driven.
Due to external pull-down circuitry CPUC will be LOW during
this stopped state.
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
CPU_STP# Deassertion
CPU_STP# Assertion
The deassertion of the CPU_STP# signal will cause all
CPUT/C outputs that were stopped to resume normal
operation in a synchronous manner. Synchronous manner
meaning that no short or stretched clock pulses will be
produces when the clock resumes. The maximum latency
from the deassertion to active outputs is no more than two
CPUC clock cycles.
When CPU_STP# pin is asserted, all CPUT/C outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped after being sampled by two
falling CPUT/C clock edges. The final state of the stopped
CPU signals is CPUT = HIGH and CPU0C = LOW. There is no
change to the output drive current values during the stopped
state. The CPUT is driven HIGH with a current value equal to
CPU_STP#
CPUT
CPUC
CPUT
CPUC
Figure 4. CPU_STP# Assertion Waveforms
CPU_STP#
CPUT
CPUC
CPUT
CPUC
Figure 5. CPU_STP# Deassertion Waveforms
Rev 1.0,November 20, 2006
Page 9 of 19
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