CY28346-2
PCI_STP# Deassertion
Three-state Control of CPU Clocks Clarification
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a high level.
During CPU_STP# and PD# modes, CPU clock outputs may
be set to driven or undriven (three-state) by setting the corre-
sponding SMBus entry in Bit6 of Byte0 and Bit6 of Byte1.
PCI_STP# Assertion
Note that the PCI STOP function is controlled by two inputs.
One is the device PCI_STP# pin number 34 and the other is
SMBus byte 0 bit 3. These two inputs to the function are
logically ANDed. If either the external pin or the internal
SMBus register bit is set low then the stoppable PCI clocks will
be stopped in a logic low state. Reading SMBus Byte 0 Bit 3
will return a 0 value if either of these control bits are set LOW
thereby indicating the devices stoppable PCI clocks are not
running.
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (tsetup). (See
Figure 2.) The PCIF (0:2) clocks will not be affected by this pin
if their control bits in the SMBus register are set to allow them
to be free running.
Table 6. Cypress Clock Power Management Truth Table
Stoppable
B0b6
B1b6
PD#
1
CPU_STP# Stoppable CPUT
CPUC
Running
Iref x6
Low
Non-Stop CPUT Non-Stop CPUC
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Running
Iref x6
Iref x2
Iref x2
Running
Hi Z
Running
Running
Iref x2
Iref x2
Running
Running
Hi Z
Running
Running
Low
1
0
0
Low
Low
1
Running
Hi Z
Running
Running
Hi Z
1
0
Hi Z
Hi Z
0
Hi Z
Hi Z
Hi Z
Hi Z
1
Running
Iref x6
Hi Z
Running
Iref x6
Hi Z
Running
Running
Hi Z
Running
Running
Hi Z
1
0
0
Hi Z
Hi Z
Hi Z
Hi Z
1
Running
Hi Z
Running
Hi Z
Running
Running
Hi Z
Running
Running
Hi Z
1
0
Hi Z
Hi Z
0
Hi Z
Hi Z
Hi Z
Hi Z
t setup
PCI_STP#
PCIF 33M
PCI 33M
Figure 6. PCI_STP# Assertion Waveforms
Rev 1.0,November 20, 2006
Page 10 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
