CY28346-2
PW R D W N#
C PU T 133M H z
C PU C 133M Hz
PC I 33M H z
AG P 66M H z
U SB 48M H z
R EF 14.318M H z
D D R T 133M H z
D D RC 133M H z
SD R AM 133M H z
Figure 2. Power-down Assertion Timing Waveforms—Unbuffered Mode
PD# Deassertion
The power-up latency between PD# rising to a valid logic ‘1’
level and the starting of all clocks is less than 3.0 ms.
30uS min
400uS max
<1.8mS
66Buff1 / GMCH
66Buff
PCIF / APIC
33MHz
PCI 33MHz
PWRDWN#
CPU 133MHz
CPU# 133MHz
3V66
66In
USB 48MHz
REF 14.318MHz
Figure 3. Power-down Deassertion Timing Waveforms
Table 5. PD# Functionality
PD#
1
DRCG
66M
66CLK (0:2)
66Input
Low
PCIF/PCI
66Input/2
Low
PCI
66Input/2
Low
USB/DOT
48M
0
Low
Low
Rev 1.0,November 20, 2006
Page 8 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
