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CY28346ZC-2 参数 Datasheet PDF下载

CY28346ZC-2图片预览
型号: CY28346ZC-2
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟合成器,差分CPU输出 [Clock Synthesizer with Differential CPU Outputs]
分类和应用: 晶体外围集成电路光电二极管时钟
文件页数/大小: 19 页 / 169 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28346-2  
Table 7. Host Clock (HCSL) Buffer Characteristics  
Characteristic  
Minimum  
Maximum  
Ro  
3000 Ohms (recommended)  
N/A  
Ros  
Vout  
N/A  
1.2V  
Table 8. CPU Clock Current Select Function  
Mult0  
Board Target Trace/Term Z  
50 Ohms  
Reference R, Iref – Vdd (3*Rr)  
Rr = 221 1%, Iref = 5.00 mA  
Rr = 475 1%, Iref = 2.32 mA  
Output Current  
Ioh = 4*Iref  
Voh @ Z  
1.0V @ 50  
0.7V @ 50  
0
1
50 Ohms  
Ioh = 6*Iref  
Table 9. Group Timing Relationship and Tolerances  
Description  
Offset  
2.5 ns  
0.0 ns  
2.5 ns  
Tolerance  
r1.0 ns  
Conditions  
3V66 to PCI  
3V66 Leads PCI (unbuffered mode)  
0 degrees phase shift  
48M_USB to 48M_DOT Skew  
66B to PCI offset  
r1.0 ns  
r1.0 ns  
66B leads PCI (buffered mode)  
Table 10.Maximum Lumped Capacitive Output Loads  
66IN to 66B Buffered Prop Delay  
Clock  
PCI Clocks  
Max Load  
Unit  
pF  
pF  
pF  
pF  
pF  
pF  
The 66IN to 66B(0:2) output delay is shown in Figure 11.  
30  
30  
30  
20  
10  
50  
The Tpd is the prop delay from the input pin (66IN) to the  
output pins (66B[0:2]). The outputs’ variation of Tpd is  
described in the AC parameters section of this data sheet. The  
measurement is taken at 1.5V.  
3V66  
66B  
48M_USB Clock  
48M_DOT  
REF Clock  
66B to PCI Buffered Clock Skew  
Figure 12 shows the difference (skew) between the 3V33(0:5)  
outputs when the 66M clocks are connected to 66IN. This  
offset is described in the Group Timing Relationship and Toler-  
ances section of this data sheet. The measurements were  
taken at 1.5V.  
USB and DOT 48M Phase Relationship  
The 48M_USB and 48M_DOT clocks are in phase. It is under-  
stood that the difference in edge rate will introduce some in  
inherent offset. When 3V66_1/VCH clock is configured for  
VCH (48-MHz) operation it is also in phase with the USB and  
DOT outputs. See Figure 10.  
3V66 to PCI Unbuffered Clock Skew  
Figure 13 shows the timing relationship between 3V66(0:5)  
and PCI(0:6) and PCIF when configured to run in the unbuf-  
fered mode.  
48MUSB  
48MDOT  
Figure 10. 48M_USB and 48M_DOT Phase Relationship  
66IN  
66B  
Tpd  
Figure 11. 66IN to 66B(0:2) Output Delay Figure  
Rev 1.0,November 20, 2006  
Page 12 of 19  
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