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CY28346ZC-2 参数 Datasheet PDF下载

CY28346ZC-2图片预览
型号: CY28346ZC-2
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟合成器,差分CPU输出 [Clock Synthesizer with Differential CPU Outputs]
分类和应用: 晶体外围集成电路光电二极管时钟
文件页数/大小: 19 页 / 169 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28346-2  
t setup  
PCI_STP#  
PCIF  
PCI  
Figure 7. PCI_STP# Deassertion Waveforms  
VID  
SEL  
VTT_PWRGD#  
PWRGD  
0.2-0.3mS  
Delay  
Wait for  
VTT_PWRGD#  
Device is not affected,  
VTT_PWRGD# is ignored.  
Sample Sels  
State 2  
VDD Clock Gen  
Clock State  
State 0  
Off  
State 1  
State 3  
On  
Clock Outputs  
Clock VCO  
On  
Off  
Figure 8. VTT_PWRGD# Timing Diagram  
S2  
S1  
VTT_PWRGD# = Low  
Delay  
>0.25mS  
Sample  
Inputs straps  
VDDA = 2.0V  
Wait for <1.8ms  
S0  
S3  
VDD3.3= off  
Normal  
Operation  
Enable Outputs  
Power Off  
VTT_PWRGD# = toggle  
Figure 9. Clock Generator Power-up/Run State Program  
Iout is selectable depending on implementation. The param-  
eters above apply to all configurations. Vout is the voltage at  
the pin of the device.  
The various output current configurations are shown in the  
host swing select functions table. For all configurations, the  
deviation from the expected output current is 7% as shown in  
the current accuracy table.  
Rev 1.0,November 20, 2006  
Page 11 of 19  
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