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CY28346ZC-2 参数 Datasheet PDF下载

CY28346ZC-2图片预览
型号: CY28346ZC-2
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟合成器,差分CPU输出 [Clock Synthesizer with Differential CPU Outputs]
分类和应用: 晶体外围集成电路光电二极管时钟
文件页数/大小: 19 页 / 169 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28346-2  
Configured as DRCG (66M), SMBus Byte0, Bit 5 = ‘0’  
Table 4. Spread Spectrum  
SS2 SS1 SS0 Spread Mode  
The default condition for this pin is to power up in a 66M  
operation. In 66M operation this output is SSCG capable and  
when spreading is turned on, this clock will be modulated.  
Spread%  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Down  
Down  
Down  
Down  
Center  
Center  
Center  
Center  
+0.00, –0.25  
+0.00, –0.50  
+0.00, –0.75  
+0.00, –1.00  
+0.13, –0.13  
+0.25, –0.25  
+0.37, –0.37  
+0.50, –1.50  
Configured as VCH (48M), SMBus Byte0, Bit 5 = ‘1’  
In this mode, the output is configured as a 48-MHz non-spread  
spectrum output. This output is phase aligned with the other  
48M outputs (USB and DOT), to within 1 ns pin-to-pin skew.  
The switching of 3V66_1/VCH into VCH mode occurs at  
system power on. When the SMBus Bit 5 of Byte 0 is  
programmed from a ‘0’ to a ‘1’, the 3V66_1/VCH output may  
glitch while transitioning to 48M output mode.  
PD# (Power-down) Clarification  
The PD# (Power-down) pin is used to shut off ALL clocks prior  
to shutting off power to the device. PD# is an asynchronous  
active LOW input. This signal is synchronized internally to the  
device powering down the clock synthesizer. PD# is an  
asynchronous function for powering up the system. When PD#  
is low, all clocks are driven to a LOW value and held there and  
the VCO and PLLs are also powered down. All clocks are shut  
down in a synchronous manner so has not to cause glitches  
while transitioning to the low ‘stopped’ state.  
Special Functions  
PCIF and IOAPIC Clock Outputs  
The PCIF clock outputs are intended to be used, if required,  
for systems IOAPIC clock functionality. ANY two of the PCIF  
clock outputs can be used as IOAPIC 33-MHz clock outputs.  
They are 3.3V outputs will be divided down via a simple  
resistive voltage divider to meet specific system IOAPIC clock  
voltage requirements. In the event these clocks are not  
required, then these clocks can be used as general PCI clocks  
or disabled via the assertion of the PCI_STP# pin.  
PD#—Assertion  
When PD# is sampled LOW by two consecutive rising edges  
of the CPUC clock, then on the next HIGH-to-LOW transition  
of PCIF, the PCIF clock is stopped LOW. On the next  
HIGH-to-LOW transition of 66Buff, the 66Buff clock is stopped  
LOW. From this time, each clock will stop LOW on its next  
HIGH-to-LOW transition, except the CPUT clock. The CPU  
clocks are held with the CPUT clock pin driven HIGH with a  
value of 2 x Iref, and CPUC undriven. After the last clock has  
stopped, the rest of the generator will be shut down.  
3V66_1/VCH Clock Output  
The 3V66_1/VCH pin has a dual functionality that is selectable  
via SMBus.  
66Buff  
PCIF  
PWRDWN#  
CPU 133MHz  
CPU# 133MHz  
3V66  
66In  
USB 48MHz  
REF 14.318MHz  
Figure 1. Power-down Assertion Timing Waveforms—Buffered Mode  
Rev 1.0,November 20, 2006  
Page 7 of 19  
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