CY28346-2
Byte 3: PCIF Clock and 48M Control Register (all bits are read and write functional)
Bit
7
@Pup
Name
48M_DOT
48M_USB
PCIF2
Description
1
1
0
48M_DOT Output Control,1 = enabled, 0 = forced LOW
48M_USB Output Control,1 = enabled, 0 = forced LOW
6
5
PCI_STP#, control of PCIF2.
0 = Free Running, 1 = Stopped when PCI_STP# is LOW
4
3
0
0
PCIF1
PCIF0
PCI_STP#, control of PCIF1.
0 = Free Running, 1 = Stopped when PCI_STP# is LOW
PCI_STP#, control of PCIF0.
0 = Free Running, 1 = Stopped when PCI_STP# is LOW
2
1
0
1
1
1
PCIF2
PCIF1
PCIF0
PCIF2 Output Control. 1=running, 0=forced LOW
PCIF1 Output Control. 1= running, 0=forced LOW
PCIF0 Output Control. 1= running, 0=forced LOW
Byte 4: DRCG Control Register(all bits are read and write functional)
Bit
7
@Pup
Name
Description
0
0
1
1
1
1
1
1
SS2 Spread Spectrum control bit (0 = down spread, 1 = center spread)
Reserved
6
5
3V66_0
3V66_0 Output Enabled. 1 = enabled, 0 = disabled
3V66_1/VCH Output Enable. 1 = enabled, 0 = disabled
3V66_5 Output Enable. 1 = enabled, 0 = disabled
66B2/3V66_4 Output Enabled. 1 = enabled, 0 = disabled
66B1/3V66_3 Output Enabled. 1 = enabled, 0 = disabled
66B0/3V66_2 Output Enabled. 1 = enabled, 0 = disabled
4
3V66_1/VCH
3V66_5
3
2
66B2/3V66_4
66B1/3V66_3
66B0/3V66_2
1
0
Byte 5: Clock Control Register (all bits are read and write functional)
Bit
7
@Pup
Name
Description
SS1 Spread Spectrum control bit
0
1
0
0
0
0
0
0
6
SS0 Spread Spectrum control bit
5
66IN to 66M delay Control MSB
4
66IN to 66M delay Control LSB
3
Reserved
2
48M_DOT edge rate control. When set to 1, the edge is slowed by 15%.
Reserved
1
0
USB edge rate control. When set to 1, the edge is slowed by 15%
Byte 6: Silicon Signature Register[2] (all bits are read-only)
Bit
7
@Pup
Name
Description
0
0
0
1
0
0
1
1
6
5
4
3
Vendor Code, 011 = IMI
2
1
0
Note:
2. When writing to this register the device will acknowledge the write operation, but the data itself will be ignored.
Rev 1.0,November 20, 2006
Page 5 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
