CY28346-2
Byte 0: CPU Clock Register
Bit @Pup Name
Description
7
0
Spread Spectrum Enable, 0 = Spread Off, 1 = Spread On. This is a Read and Write control bit.
CPU clock Power-down Mode Select.
0 = Drive CPUT(0:2) to 4 or 6 IREF and drive CPUC(0:2) to low when PD# is asserted LOW.
1 = Three-state all CPU outputs. This is only applicable when PD# is LOW. It is not applicable to
CPU_STP#.
6
0
3V66_1/VCH 3V66_1/VCH frequency Select, 0 = 66M selected, 1 = 48M selected
This is a Read and Write control bit.
5
4
3
0
Pin 53 CPUT,CPUC CPU_STP#. Reflects the current value of the external CPU_STP# (pin 53) This bit is Read-only.
PCI
Reflects the current value of the internal PCI_STP# function when read. Internally PCI_STP# is
a logical AND function of the internal SMBus register bit and the external PCI_STP# pin.
Pin 34
2
1
0
Pin 40
Pin 55
Pin 54
Frequency Select Bit 2. Reflects the value of SEL2 (pin 40). This bit is Read-only.
Frequency Select Bit 1. Reflects the value of SEL1 (pin 55). This bit is Read-only.
Frequency Select Bit 0. Reflects the value of SEL0 (pin 54). This bit is Read-only.
Byte 1: CPU Clock Register
Bit @Pup
Name
Description
7
Pin 43
MULT0
MULT0 (Pin 43) Value. This bit is Read-only.
Controls functionality of CPUT/C(0:2) outputs when CPU_STP# is asserted. 0 = Drive CPUT(0:2) to
4 or 6 IREF and drive CPUC(0:2) to low when CPU_STP# asserted LOW. 1 = Three-state all CPU
outputs. This bit will override Byte0, Bit6 such that even if it is a 0, when PD# goes low the CPU outputs
will be three-stated.
6
0
CPU_STP#
Controls CPU2 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
CPUT2
CPUC2
5
4
3
0
0
0
Controls CPU1 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
CPUT1
CPUC1
Controls CPUT0 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
CPUT0
CPUC0
CPUT2 CPUT/C2 Output Control, 1 = enabled, 0 = disable HIGH and CPUC2 disables LOW
CPUC2 This is a Read and Write control bit.
2
1
0
1
1
1
CPUT1 CPUT/C1 Output Control, 1 = enabled, 0 = disable HIGH and CPUC1 disables LOW
CPUC1 This is a Read and Write control bit.
CPUT0 CPUT/C0 Output Control, 1 = enabled, 0 = disable HIGH and CPUC0 disables LOW
CPUC0 This is a Read and Write control bit.
Byte 2: PCI Clock Control Register (all bits are read and write functional)
Bit
7
@Pup
Name
REF
Description
0
1
1
1
1
1
1
1
REF Output Control. 0 = high strength, 1 = low strength
PCI6 Output Control. 1 = enabled, 0 = forced LOW
PCI5 Output Control. 1 = enabled, 0 = forced LOW
PCI4 Output Control. 1 = enabled, 0 = forced LOW
PCI3 Output Control. 1 = enabled, 0 = forced LOW
PCI2 Output Control. 1 = enabled, 0 = forced LOW
PCI1 Output Control. 1 = enabled, 0 = forced LOW
PCI0 Output Control. 1 = enabled, 0 = forced LOW
6
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
5
4
3
2
1
0
Rev 1.0,November 20, 2006
Page 4 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
