CY28346-2
Pin Description (continued)
Pin
Name
VSSIREF
PWR
I/O
Description
41
26
–
PWR Current reference programming input for CPU buffers. A resistor is
connected between this pin and IREF. This pin should also be returned
to device VSS.
VDDA
–
PWR Analog power input. Used for PLL and internal analog circuits. It is also
specifically used to detect and determine when power is at an acceptable
level to enable the device to operate.
Serial Data Interface
Data Protocol
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
The clock driver serial protocol accepts block write and block
read operations from the controller. For block write/read
operation, the bytes must be accessed in sequential order
from lowest to highest byte (most significant bit first) with the
ability to stop after any complete byte has been transferred.
The block write and block read protocol is outlined in Table 2.
The slave receiver address is 11010010 (D2h).
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
1
Description
Bit
1
Description
Start
Start
2:8
9
Slave address – 7 bits
Write = 0
2:8
9
Slave address – 7 bits
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bit
‘00000000’ stands for block operation
11:18
Command Code – 8 bit
‘00000000’ stands for block operation
19
20:27
28
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
......................
19
20
Acknowledge from slave
Repeat start
21:27
28
Slave address – 7 bits
Read = 1
29:36
37
29
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge
38:45
46
30:37
38
....
39:46
47
Data byte from slave – 8 bits
Acknowledge
....
Data Byte (N–1) –8 bits
Acknowledge from slave
Data Byte N –8 bits
Acknowledge from slave
Stop
....
48:55
56
Data byte from slave – 8 bits
Acknowledge
....
....
....
Data bytes from slave/Acknowledge
Data byte N from slave – 8 bits
Not Acknowledge
....
....
....
....
Stop
Rev 1.0,November 20, 2006
Page 3 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
