CY28346-2
Absolute Maximum Conditions
Parameter
VDD
Description
Core Supply Voltage
Condition
Min.
–0.5
–0.5
–0.5
–65
0
Max.
4.6
Unit
V
VDD_A
VIN
Analog Supply Voltage
Input Voltage
4.6
V
Relative to VSS
VDD + 0.5
150
85
VDC
°C
TS
Temperature, Storage
Non-functional
TA
Temperature, Operating Ambient
Temperature, Junction
Functional
°C
TJ
Functional
–
150
45
°C
ØJC
Dissipation, Junction to Case
Dissipation, Junction to Ambient
Mil-Spec 883E Method 1012.1
JEDEC (JESD 51)
–
°C/W
°C/W
V
ØJA
–
15
ESDHBM
Ul-94
MSL
ESD Protection (Human Body Model) MIL-STD-883, Method 3015
2000
–
–
Flammability Rating
V–0 @1/8 in.
10
ppm
Moisture Sensitivity Level
1
DC Parameters (VDD = VDDA = 3.3V 5%)
Parameter Description
Idd3.3V Dynamic Supply Current
Ipd3.3V Power-down Supply Current PD# Asserted
Conditions
All frequencies at maximum values[3]
Min.
Typ.
Max.
Unit
280
mA
mA
pF
Note 4
Cin
Cout
Lpin
Cxtal
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
5
6
pF
7
nH
pF
Crystal Pin Capacitance
Measured from the Xin or Xout Pin to Ground.
30
36
42
AC Parameters (VDD = VDDA = 3.3V 5%)
66 MHz
100 MHz
133 MHz
200 MHz
Min. Max. Unit
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Notes
Crystal
Tdc
Xin Duty Cycle
Xin Period
47.5
69.84
0.7Vdd
0
52.5
71.0
47.5
69.84
0.7Vdd
0
52.5
71.0
47.5
69.84
0.7Vdd
0
52.5
71.0
47.5
69.84
0.7Vdd
0
52.5
71.0
%
ns
V
5, 6, 7
Tperiod
Vhigh
Vlow
5, 8, 9, 6
Xin High Voltage
Xin Low Voltage
Vdd
Vdd
Vdd
Vdd
0.3Vdd
10.0
0.3Vdd
10.0
0.3Vdd
10.0
0.3Vdd
10.0
V
Tr/Tf
Xin Rise and Fall
Times
ns
10
Tccj
Xin Cycle to Cycle
Jitter
500
500
500
500
ps
8, 11, 6
CPU at 0.7V Timing
Tdc
CPUT and CPUC
Duty Cycle
45
55
45
55
45
55
45
55
%
11, 12, 13
11, 12, 13
Tperiod
CPUT and CPUC
Period
14.85
15.3
9.85
10.2
7.35
7.65
4.85
5.1
ns
Notes:
3. All outputs loaded as per maximum capacitive load table.
4. Absolute value = ((Programmed CPU Iref) x (2)) + 10 mA.
5. This parameter is measured as an average over 1-Ps duration, with a crystal center frequency of 14.31818 MHz
6. When Xin is driven from an external clock source.
7. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock
duty cycle will not be within data sheet specifications.
8. All outputs loaded as perTable 10.
9. Probes are placed on the pins and measurements are acquired at 1.5V for 3.3V signals (see test and measurement set-up section of this data sheet).
10. Measured between 0.2Vdd and 0.7Vdd.
11. This measurement is applicable with Spread ON or Spread OFF.
12. Measured at crossing point (Vx) or where subtraction of CLK-CLK# crosses 0 volts Measured from Vol = 0.175V to Voh = 0.525V.
13. Test load is Rta = 33.2 ohms, Rd = 49.9 ohms.
Rev 1.0,November 20, 2006
Page 14 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
