CXD1968AR
CRL_FREQ_1
Read Only
Offset Address: 0x20
Bit
Name
Description
Default R/W
7:0 CRL Frequency Offset Current (or latched) bits 7:0 of CRL frequency offset
—
R
CRL_FREQ_2
Read Only
Offset Address: 0x21
Bit
Name
Description
Default R/W
7:0 CRL Frequency Offset Current (or latched) bits 15:8 of CRL frequency offset
—
R
CRL_FREQ_3
Read Only
Offset Address: 0x22
Bit
7
Name
Description
Default R/W
Sign extension:
CRL frequency offset (23) ≤ CRL frequency offset (22)
SEXT
—
—
R
R
6:0 CRL Frequency Offset Current (or latched) bits 22:16 of CRL frequency offset
Note) 1. Refer to PIR_CTL register description for details of the latched mode.
2. The following relationships are defined:
The carrier offset in FFT bins is equal to CRL frequency offset / 4096.
For 2K mode, the carrier offset frequency (Hz) is equal to;
CRL frequency offset × 1.0899 in 8MHz channel
CRL frequency offset × 0.9537 in 7MHz channel
CRL frequency offset × 0.8174 in 6MHz channel
For 8K mode, the carrier offset frequency (Hz) is equal to;
CRL frequency offset × 0.2725 in 8MHz channel
CRL frequency offset × 0.2384 in 7MHz channel
CRL frequency offset × 0.2044 in 6MHz channel
3. The value read back from the combined CRL_FREQ_1, CRL_FREQ_2, CRL_FREQ_3 registers
in the CXD1968AR and CXD1976R is 1/4 of the value read back by the same registers in the
CXD1973Q due to the increased frequency offset search range of the CXD1968AR and
CXD1976R.
4. CRL frequency offset is a signed quantity, in two’s complement format.
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SONY [ SONY CORPORATION ]
