CXD1968AR
TRL_TIME_1
Read Only
Offset Address: 0x1D
Bit
Name
Description
Default R/W
7:0 TRL Timing Offset Current (or latched) bits 7:0 of TRL timing offset
—
R
TRL_TIME_2
Read Only
Offset Address: 0x1E
Bit
Name
Description
Default R/W
7:0 TRL Timing Offset Current (or latched) bits 15:8 of TRL timing offset
—
R
Note) 1. Refer to PIR_CTL register description for details of the latched mode. The timing offset in ppm
is equal to;
Offset (ppm) = 1e6 × TRL timing offset / TRL_NOMINALRATE / 16
Example: for 8MHz OFDM using a 20.48MHz crystal
Offset (ppm) = TRL timing offset / 239.67
2. TRL timing offset is a signed quantity, in two’s complement format.
CRL_CTL
Read/Write
RESET: 0x24
Default R/W
Offset Address: 0x1F
Bit
7
Name
Description
Set to disable SYR fine offset correction on CRL during
acquisition.
CRL Disable Fine
0
R/W
R/W
Additional gain (x/16) applied during tracking (default is
to reduce gain by 1/4 during tracking).
6:3 CRL Track Gain Factor
2:0 CRL Loop Gain
0100
Sets the gain (x/16) of the carrier loop during acquisition.
Also sets the gain (combined with CRL track gain factor)
during tracking.
100
R/W
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SONY [ SONY CORPORATION ]
