CXD1968AR
TRL_CTL
Read/Write
RESET: 0x14
Default R/W
Offset Address: 0x1A
Bit
7
Name
Reserved
Description
0
R/W
R/W
Additional gain (x/16) applied during tracking (default is
to reduce gain by 1/8 during tracking).
6:3 TRL Track Gain Factor
2:0 TRL Loop Gain
0010
Sets the gain (x/16) of the sample timing loop during
acquisition. Also sets the gain (combined with TRL track
gain factor) during tracking.
100
R/W
TRL_NOMINALRATE_1
Read/Write
RESET: 0x00
Offset Address: 0x1B
See table below for recommended values.
Description Default R/W
Bit
Name
7:0 TRL Nominal Rate Bits 15:8 of TRL nominal rate
00h
R/W
TRL_NOMINALRATE_2
Read/Write
RESET: 0x80
See table below for recommended values.
Description Default R/W
Offset Address: 0x1C
Bit
Name
7:0 TRL Nominal Rate Bits 23:16 of TRL nominal rate
80h
R/W
Note) 1. The TRL_NOMINALRATE is a 24-bit non-contiguous register comprising three 8-bit registers
called TRL_NOMINALRATE_2, TRL_NOMINALRATE_1 and TRL_NOMINALRATE_0.
Also see the TRL_NOMINALRATE_0 register at address 0x65.
2. Sets the nominal rate of the sample timing NCO. This can be used to allow reduced bandwidth
(6 and 7MHz) operation without changing crystal or tuner clock reference frequencies.
TRL nominal rate is the ratio of the FFT time sample clock to the (fixed) ADC clock frequency.
16 × ChanBW
24
--------------------------------------
TRLNOMINALRATE =
× (2 )
FADC × 7
The maximum allowable value of this register is 16777215. The minimum TRL nominal rate is 11184810.66
= AAAAABh. Some common settings are given below for a 20.48MHz crystal supplying the ADC clock, or
from a 20.5MHz ADC clock derived from the PLL output.
Channel bandwidth
8MHz
FADC = 20.48MHz
14979657 (E49249h)
13107200 (C80000h)
11234743 (AB6DB7h)
FADC = 20.5MHz
14965043 (E45933h)
13094412 (C7CE0Ch)
11223782 (AB42E6h)
7MHz
6MHz
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SONY [ SONY CORPORATION ]
