CXD1968AR
9. Control Register Definitions
Register Map
Name
Addr. R/W
7
6
5
4
3
2
1
0
CXD1968AR COFDM Core Registers
COR_CTL
00 R/W
01
Reserved
Core Active
Hold
Core State[3:0]
Core State[3:0]
CHC
Tracking
SYR
Locked
AGC
Locked
COR_STAT
R
TPS Locked
Reserved
INTENAGC INTEN TPS INTEN TPS INTEN TPS
INTEN
Global
INTENSYR INTEN FFT
SymEnd
COR_INTEN
02 R/W
03 R/W
Lock
Change
RCVD
RCVD
RCVD
Update
Done
BCHBad
Changed
INTSTAT
SYR
SymEnd
INTSTAT
AGC Lock
Change
INTSTAT
TPS
INTSTAT
TPS RCVD TPS RCVD
INTSTAT
INTSTAT
FFT Done
COR_INTSTAT
Reserved
BadBCH
Changed
Update
COR_MODEGUARD
AGC_CTL
04 R/W ZIF Enable
Reserved
Force
Mode
Guard
AGC Use
Last Value
05 R/W
Delay Startup[7:5]
Reserved
AGC BW Reduction[1:0] AGC Neg
AGC Set
06 R/W
07 R/W
08 R/W
09 R/W
AGC Manual[7:0]
AGC_MANUAL
AGC_TARGET
AGC Manual[11:8]
AGC Gain I[11:8]
AGC Target[7:0]
AGC Gain I[7:0]
AGC_GAIN
AGC After
DCC
AGC
Locked
0A R/W
0B R/W
Lock Q
Lock I
ITB Invert
Spectrum
ITB_CTL
Reserved
0C R/W
0D R/W
ITB Frequency[7:0]
ITB_FREQ
CAS_CTL
Reserved
ITB Frequency[13:8]
CCS
ACS
DAGC
Disable
DAGC BW
Reduction[1:0]
0E R/W
0F R/W
CCSMU[2:0]
Enable
Disable
CAS_FREQ
CAS_DAGCGAIN
TEST9
CCS Freq[7:0]
10
R
CAS DAG Gain[7:0]
11 R/W TEST9[7]
TEST9[6:3]
TEST9[2] TEST9[1] TEST9[0]
SYR
Locked
SYR_STAT
FFT_CTL
12
R
Reserved
TEST5
Reserved SYR Mode
SYR Guard[1:0]
FFT Test FFTManual FFTInverse
Trigger
17 R/W
Reserved
Mode
Transform
SCR No
Common
Phase
SCR
Disable
SCR_CTL
PPM_CTL
18 R/W Reserved
19 R/W Reserved
SYR Adjust Decay[2:0]
Reserved
PPM
Reduced
Search
Time
PPM
Disable
Find
Scattered
Pilots
PPM
Bypass
Corr
PPMMaxFreq[2:0]
Reserved
Enable
TRL_CTL
1A R/W Reserved
1B R/W
TRL Track Gain Factor[3:0]
TRL Loop Gain[2:0]
TRL_NOMINALRATE_1
TRL_NOMINALRATE_2
TRL Nominal Rate[15:8]
TRL Nominal Rate[23:16]
TRL Timing Offset[7:0]
TRL Timing Offset[15:8]
1C R/W
1D
1E
R
R
TRL_TIME
CRL_CTL
CRL
Disable
Fine
1F R/W
CRL Track Gain Factor[3:0]
CRL Loop Gain[2:0]
20
21
22
R
R
R
CRL Frequency Offset[7:0]
CRL Frequency Offset[15:8]
CRL Frequency Offset[22:16]
CRL_FREQ
Sign Ext
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