CXD1185CQ/CR
1-4-1. Interrupt request register 1 (R2 : R)
This register’s interrupt conditions can be masked in the interrupt authorization register 1.
When one of the bits in this register is set, MIRQ bit in the status register and IRQ signal are set. If the
interrupt bit is authorized in the interrupt authorization register 1, the IRQ pin is activated simultaneously.
7
6
5
4
3
2
1
0
STO
RSL
SWA SWOA ARBF
STO
RSL
: Selection Time Over
Indicates a time-out error during selection. Also, indicates that the SCSI bus RST signal has been
driven for the time set in the selection/reset timer if the mode register bit 4 (TMSL) is set to “1”. The
selection time-out time and SCSI bus RST signal drive time are determined by the value of the
selection/reset timer register.
: Reselected
Indicates that reselection has taken place. FNC bit in the interrupt register 2 is set after reselection.
The CPU may not write new commands to the command register until the FNC bit is set. This bit is
not set unless the “Enable Selection/Reselection” command is executed.
SWA : Selection With ATN
Indicates that selection has taken place with the SCSI bus ATN signal driven. FNC bit in the
interrupt register 2 is set after selection. The CPU may not write new commands to the command
register until the FNC bit is set. This bit is not set unless the “Enable Selection/Reselection”
command is executed.
SWOA : Selection Without ATN
Indicates that the selection has taken place. FNC bit in the interrupt register 2 is set after selection.
The CPU may not write new commands to the command register until the FNC bit is set. This bit is
not set unless the “Enable Selection/Reselection” command is executed.
ARBF : Arbitration Fail
Indicates that the CXD1185C lost in the arbitration for the right to use the SCSI bus. This bit is set
when, after receiving a selection/reselection command, the chip waited for bus free and entered
arbitration only to be encountered by another device with higher priority. As soon as this bit is set
the selection/reselection command is terminated. To participate in another arbitration a new
selection/reselection command must be written to the command register.
1-4-2. Interrupt request register 2 (R3 : R)
This register’s interrupt conditions can be masked in the interrupt authorization register 2.
When one of the bits in this register is set, MIRQ bit in the status register and IRQ signal are set. If the
interrupt bit is authorized in the interrupt authorization register 2, the IRQ pin is activated simultaneously.
7
6
5
4
3
2
1
0
FNC
DCNT SRST
PHC
DATN
DPE
SPE RMSG
FNC
: Function Complete
Indicates that the received command was executed and terminated.
DCNT : Disconnected
Indicates that a disconnect has taken place in the initiator mode.
SRST : SCSI Reset
Indicates that the SCSI bus RST pin was driven. This bit is also set when the “Assert RST”
command is executed.
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SONY [ SONY CORPORATION ]
