CXD1185CQ/CR
1-2. Command register (R0 : W)
This is the register to which CXD1185C commands are written.
When a command is written to this register, status register bit 0 (CIP) is set. When the command is executed
and terminated, interrupt request register 2 bit 7 (FNC) is set, and the CIP bit and command register are
cleared.
7
6
5
4
3
2
1
0
CAT1 CAT0
DMA
TRBE CMD3 CMD2 CMD1 CMD0
CAT1, CAT0 :
Sets the category code given to the CXD1185C.
CXD1185C commands are divided into the following four categories :
CAT1
CAT0
Mode
0
0
1
1
0
1
0
1
Commands which are valid in any status
Commands which are valid in disconnected status
Commands which are valid in target status
Commands which are valid in initiator status
If the current status of the CXD1185C does not match with the category code in the command
received, the CIP and command registers are cleared. No interrupt is generated in this case.
DMA : DMA mode
When this bit is set to “1” and a transfer command is executed, DMA transfer takes place via the
data bus (D7-D0). During the DMA transfer, any attempts by the CPU to read/write SCSI data
register via CPU bus is ignored.
TRBE : Activates the transfer byte counter.
When this bit is set to “1” and a transfer command is executed, the transfer byte counter is
decremented each time a byte of data is transferred.
When the counter reaches “0” the next data request is stopped. At this point, if the mode where the
data is output to SCSI or DMA mode is “1”, the CXD1185C will continue to transfer any data
remaining in FIFO until it is empty. If a transfer command is executed when this bit is set to “0”, 1
byte of data will be transferred regardless of the value of the transfer byte counter and the
command will be terminated. In this case the transfer byte counter is not decremented. When DMA
bit is set, TRBE bit must also be set. These two bits can be set simultaneously during command
write.
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SONY [ SONY CORPORATION ]
