CXA3106Q
2. HOLD timing
SYNC input
(SYNC POL = 1)
SYNC input
(SYNC POL = 0)
DIVOUT output
(TTL)
Thh Ths
Thh Ths
HOLD input
(TTL)
Thold
The phase comparison output is held and fixed VCO output frequency is output.
CLK output
HOLD signal set-up time (Ths) is a time from the rising edge of HOLD signal to the falling edge of DIVOUT.
Or, when SYNC POL = 1, it is a time from the falling edge of HOLD signal to the rising edge of SYNC; when
SYNC POL = 0, it is the time from the falling edge of HOLD signal to the falling edge of SYNC.
HOLD signal hold time (Thh) is the time from the falling edge of DIVOUT to falling edge of HOLD signal. Or,
when SYNC POL = 1, it is the time from the rising edge of SYNC to the rising edge of HOLD signal; when
SYNC POL = 0, it is the time from the falling edge of SYNC to the rising edge of HOLD signal.
When the HOLD input is held, the CLK frequency fluctuation can be calculated as follows.
∆V
+Q –Q
I
C
SW
∆f
VCO
Ileak
SW
I
C · ∆V = Q = Ileak · Thold
C:
Loop filter capacitance
Voltage variation due to leak current
∆V:
Ileak: Internal amplifier leak current
Thold: Hold time
∆V = Ileak · Thold/C
∆f = ∆V · KVCO = Ileak · Thold/C · KVCO
For example, assuming f = 100MHz, Ileak = 1nA, Thold = 1ms, C = 0.33µF, and KVCO = 2π · 50MHz/V, then:
∆V = 1 × 10–9 · 1 × 10–3/(0.33 × 10–6) = 3 × 10–6 [V]
∆f = 1 × 10–9 · 1 × 10–3/(0.33 × 10–6) · 50 × 106 = 151 [Hz]
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SONY [ SONY CORPORATION ]
