CXA3106Q
3. UNLOCK timing
Inside the IC Outside the IC
VCC
I2
R2
C
R1
I1
UNLOCK
S2
S1
unlock
detect
Signal from phase
comparator
The unlock detect output is an open collector. When unlock detect output S1 goes high, the current I1 is pulled in.
The UNLOCK sensitivity can be adjusted by connecting external resistors (R1, R2) and a capacitor (C) to this output
pin as appropriate and changing these values. Operation during three modes is described below.
CASE 1: When there is no phase difference, that is to say, when the PLL is locked.
The S1 signal is low and the S2 signal is high.
The UNLOCK output remains low.
S1
S2
threshold
level
UNLOCK
CASE 2: When there is a phase difference, that is to say, when the S1 signal goes high and low as shown in
the figure below, the fall slew rate of the S2 signal is determined by the current I1 flowing into that
open collector. Therefore, increasing the resistance R1 causes the S2 signal fall slew rate to
become slower. Also, since the S2 signal rise slew rate is determined by the current I2, reducing
the resistance R2 causes the S2 signal rise slew rate to become faster. If this integrated S2 signal
does not fall below the threshold level of the next inverter, the UNLOCK signal stays low, and the
PLL is said to be locked.
S1
S2
threshold
level
UNLOCK
CASE 3: However, even if a phase difference exists as shown above, if the resistance R1 is reduced, the
current I1 flowing into the open collector increases, and the S2 signal fall slew rate becomes faster.
Also, if the resistance R2 is increased, the S2 signal rise slew rate becomes slower. If this
integrated S2 signal falls below the threshold level of the next inverter, the UNLOCK signal goes
from low to high, and the PLL is said to be unlocked.
S1
threshold
level
S2
UNLOCK
– 25 –
SONY [ SONY CORPORATION ]
