CXA2101AQ
HSEP-SEL
FIX-SYNC
(1) : Sync separation system setting (valid for YG-IN (Pin 26) input)
0 = Forced slice at sync tip + 0.15V level
1 = Charging/discharging for duty cycle
(2) : Switch for setting sync identification circuit operation mode to auto or fixed.
0 = Automatic identification (with priority sequence)
1 = Independent H, V sync signals used
2 = Composite sync input used
3 = Sync on Y, sync on Green input used
V-TC
(2) : Setting for V sync separation time constant
0 = 6µs
1 = 8µs
2 = 12µs
3 = 18µs
H-WIDTH
(2) : Setting of output pulse width to HS-OUT and clamping pulse generation block.
When the pulse width of the input sync signal is wider than the pulse width in each data,
the wider of the two pulses is output.
SELH-OUT
0 = THRUGH
1 = 1.4µs
Clamping pulse generation block
0 = 1.4µs
1 = 1.4µs
2 = 1.7µs
3 = 3.7µs
2 = 1.7µs
3 = 3.7µs
HHD-TC
(1) : Setting of H sync separation time constant for YG-IN (Pin 26) input
0 = Time constant for input complying with HD-TV standard
1 = Time constant for input complying with any other HD-TV standard
HS-MASK
(1) : Setting for whether H sync is to be added in V sync at HS-OUT (Pin 29) and SELH-OUT
(Pin 79)
0 = Not added
1 = Added
CR OFFSET 1 (4) : For canceling the offset between CrCb of IN1 and SELIN systems
0h = –10mV
7h = 0mV
Fh = +12mV
∗
These variable range is DC variation amount of respective input pins.
CB OFFSET 1 (4) : For canceling the offset between CrCb of IN1 and SELIN systems
0h = –10mV
7h = 0mV
Fh = +12mV
∗
These variable range is DC variation amount of respective input pins.
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SONY [ SONY CORPORATION ]
