CXA2101AQ
Description of Operation
1. Programmable matrix selector
This IC contains video switching circuits for 4 systems, and they are selected by INPUT-SEL (I2C bus). YCbCr,
HD YPbPr, GBR and the respective HV sync signals can be supplied as the input of each system.
As the multiscan compatible range, signals can be input at a horizontal scanning frequency from 15kHz to
60kHz. The selected signals are output to SEL-OUT (Pins 76, 77, 79 and 80), and they can be connected to
the external processor, etc. When the signals are to be input again to the IC, they are supplied through the
clamp capacitor to the SEL-IN (Pins 62, 63 and 64) system.
Both positive and negative polarities are supported by the HV sync signal input.
Select MAT-OUT (I2C bus) as follows in accordance with the input signals.
• When the YCbCr signals are input, select the THROUGH1 mode.
• When the YPbPr and GBR signals are input, select the mode which converts them into YCbCr signals.
• When the GBR signals are input, they can be output directly to the internal RGB system signal processing.
A DC voltage of approximately 4V is output to SEL-OUT at this time.
The matrix conversion formulas are shown below.
[MAT OUT = 1: YHD PbPr → YCbCr]
Y = YHD + 0.0938Pb + 0.196Pr
Cb = 0.564 (1.762Pb – 0.196Pr)
Cr = 0.713 (–0.0938Pb + 1.379Pr)
[MAT OUT = 2: GBR → YCbCr]
Y = 0.299R + 0.587G + 0.114B
Cb = 0.564 (–0.299R – 0.587G + 0.886B)
Cr = 0.713 (0.701R – 0.587G – 0.114B)
The HV sync signal processing system will now be described.
First, whether the selected sync signals have been input from the H and V pins is identified, and the results are
sent as EH and EV to the status register as the existence status data. Meanwhile, the H and V signals pass
through the polarity identification circuit where their polarities are aligned, and then they are input to the priority
level circuit.
When the composite sync (CS) signal is to be input, input it to the H input pin in each input system. After the
signals have passed through the polarity identification circuit, the V sync signal is separated, and it enters the
priority level circuit.
When sync on Y or sync on Green signal is to be input, input it to Pin 3 in each input system.
After passing through HYSW, the signal is amplified by 6dB and output to YG-OUT (Pin 25). The output is then
returned to YG-IN (Pin 26) through the sync tip clamp capacitor, the sync signal is separated, and it enters the
priority level circuit. By setting HYSW (I2C bus) to 1, this route can be used also when the CS signal is input.
In this way, the respective sync signals are input to the priority level circuit, and the sync signals to be output in
the EH and EV status are determined.
The priority levels are shown below. When designing a TV set, ensure that one of the following 3 conditions
applies.
1. When both HV signals are present at the HV pins, give top priority to the selection of these signals.
→ EH = 1; EV = 1
2. When the CS signal is present at the H pin and no input signal is present at the V pin, the CS signal is
selected.
3. When the Y or Green is present at Pin 3 and no input signal is present at the HV pin, the Y or Green signal
is selected. → EH = 0; EV = 0
→ EH = 1; EV = 0
When the HV output is determined, the pulse width of the H sync signal is adjusted by H WIDTH (I2C bus), and
the H sync signal is output along with the V sync signal to SEL-OUT. HS-OUT and VS-OUT (Pins 28 and 29)
are provided to enable these sync signals and the HV input signals (Pins 65 and 66) of the IN1 system to be
selected by YCBCR/MAT (I2C bus) and output.
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SONY [ SONY CORPORATION ]
