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SP37E760 参数 Datasheet PDF下载

SP37E760图片预览
型号: SP37E760
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3 V的I / O控制器的嵌入式应用 [3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS]
分类和应用: 控制器
文件页数/大小: 78 页 / 507 K
品牌: SMSC [ SMSC CORPORATION ]
 浏览型号SP37E760的Datasheet PDF文件第21页浏览型号SP37E760的Datasheet PDF文件第22页浏览型号SP37E760的Datasheet PDF文件第23页浏览型号SP37E760的Datasheet PDF文件第24页浏览型号SP37E760的Datasheet PDF文件第26页浏览型号SP37E760的Datasheet PDF文件第27页浏览型号SP37E760的Datasheet PDF文件第28页浏览型号SP37E760的Datasheet PDF文件第29页  
BIT 2  
BIT 3  
BIT 4  
BIT 5  
BIT 6  
FIFOs Enabled FIFOs  
(Note 5) Enabled (Note  
5)  
BIT 7  
Interrupt ID Bit Interrupt ID Bit  
0
0
(Note 5)  
XMIT FIFO  
Reset  
DMA Mode  
Select (Note  
6)  
Reserved  
Reserved  
RCVR Trigger RCVR Trigger  
LSB  
Stick Parity Set Break  
MSB  
Number of  
Stop Bits  
(STB)  
Parity Enable Even Parity  
Divisor Latch  
Access Bit  
(DLAB)  
(PEN)  
Select (EPS)  
OUT1  
(Note 3)  
OUT2  
(Note 3)  
Loop  
0
0
0
Parity Error  
Framing Error Break  
Transmitter Transmitter  
Error in  
(PE)  
(FE)  
Interrupt (BI) Holding  
Empty (TEMT) RCVR FIFO  
Register  
(Note 2)  
(Note 5)  
(THRE)  
Trailing Edge Delta Data  
Clear to  
Data Set  
Ring Indicator  
(RI)  
Data Carrier  
Ring Indicator Carrier Detect Send (CTS) Ready  
Detect (DCD)  
(TERI)  
Bit 2  
(DDCD)  
Bit 3  
(DSR)  
Bit 5  
Bit 5  
Bit 4  
Bit 4  
Bit 12  
Bit 6  
Bit 6  
Bit 14  
Bit 7  
Bit 7  
Bit 15  
Bit 2  
Bit 3  
Bit 10  
Bit 11  
Bit 13  
Note 3: This bit no longer has a pin associated with it.  
Note 4: When operating in the XT mode, this register is not available.  
Note 5: These bits are always zero in the non-FIFO mode.  
Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip.  
4.4 Notes On Serial Port FIFO Mode Operation  
4.4.1 GENERAL  
The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected.  
4.4.2 TX AND RX FIFO OPERATION  
The Tx portion of the UART transmits data through TXD as soon as the CPU loads a byte into the Tx FIFO. The  
UART will prevent loads to the Tx FIFO if it currently holds 16 characters. Loading to the Tx FIFO will again be  
enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely  
autonomous operation of the Tx.  
The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt whenever the Tx  
FIFO is empty and the Tx interrupt is enabled, except in the following instance. Assume that the Tx FIFO is empty  
and the CPU starts to load it. When the first byte enters the FIFO the Tx FIFO empty interrupt will transition from  
active to inactive. Depending on the execution speed of the service routine software, the UART may be able to  
transfer this byte from the FIFO to the shift register before the CPU loads another byte. If this happens, the Tx FIFO  
will be empty again and typically the UART’s interrupt line would transition to the active state. This could cause a  
system with an interrupt control unit to record a Tx FIFO empty condition, even though the CPU is currently servicing  
that interrupt. Therefore, after the first byte has been loaded into the FIFO the UART will wait one serial  
character transmission time before issuing a new Tx FIFO empty interrupt.  
This one character Tx interrupt delay will remain active until at least two bytes have been loaded into the  
FIFO, concurrently. When the Tx FIFO empties after this condition, the Tx interrupt will be activated without  
a one character delay.  
Rx support functions and operation are quite different from those described for the transmitter. The Rx FIFO receives  
data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if Rx interrupts are  
enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it holds 16 of  
them. It will not accept any more data when it is full. Any more data entering the Rx shift register will set the Overrun  
SMSC DS – SP37E760  
Page 25  
Rev. 04/13/2001  
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