欢迎访问ic37.com |
会员登录 免费注册
发布采购

SP37E760 参数 Datasheet PDF下载

SP37E760图片预览
型号: SP37E760
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3 V的I / O控制器的嵌入式应用 [3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS]
分类和应用: 控制器
文件页数/大小: 78 页 / 507 K
品牌: SMSC [ SMSC CORPORATION ]
 浏览型号SP37E760的Datasheet PDF文件第20页浏览型号SP37E760的Datasheet PDF文件第21页浏览型号SP37E760的Datasheet PDF文件第22页浏览型号SP37E760的Datasheet PDF文件第23页浏览型号SP37E760的Datasheet PDF文件第25页浏览型号SP37E760的Datasheet PDF文件第26页浏览型号SP37E760的Datasheet PDF文件第27页浏览型号SP37E760的Datasheet PDF文件第28页  
1. Bit 0=1 as long as there is one byte in the RCVR FIFO.  
2. Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as when in  
the interrupt mode, the IIR is not affected since EIR bit 2=0.  
3. Bit 5 indicates when the XMIT FIFO is empty.  
4. Bit 6 indicates that both the XMIT FIFO and shift register are empty.  
5. Bit 7 indicates whether there are any errors in the RCVR FIFO.  
There is no trigger level reached or time-out condition indicated in the FIFO Polled Mode, however, the RCVR and  
XMIT FIFOs are still fully capable of holding characters.  
Table 11 - Individual UART Channel Register Summary  
REGISTER  
ADDRESS*  
REGISTER  
SYMBOL  
REGISTER NAME  
BIT 0  
BIT 1  
ADDR = 0  
DLAB = 0  
ADDR = 0  
DLAB = 0  
ADDR = 1  
DLAB = 0  
Receive Buffer Register  
RBR  
THR  
IER  
Data Bit 0 (Note Data Bit 1  
(Read Only)  
1)  
Transmitter Holding  
Register (Write Only)  
Interrupt Enable Register  
Data Bit 0  
Data Bit 1  
Enable Received  
Data Available  
Enable Transmitter  
Holding Register  
Empty Interrupt  
(ETHREI)  
Interrupt (ERDAI)  
ADDR = 2  
Interrupt Ident. Register  
(Read Only)  
IIR  
”0” if Interrupt  
Pending  
Interrupt ID Bit  
ADDR = 2  
ADDR = 3  
FIFO Control Register  
FCR  
LCR  
FIFO Enable  
RCVR FIFO Reset  
(Write Only)  
Line Control Register  
Word Length  
Select Bit 0  
(WLS0)  
Word Length  
Select Bit 1  
(WLS1)  
ADDR = 4  
MODEM Control Register  
MCR  
Data Terminal  
Request to Send  
Ready (DTR)  
(RTS)  
ADDR = 5  
ADDR = 6  
Line Status Register  
MODEM Status Register  
LSR  
MSR  
Data Ready (DR)  
Overrun Error (OE)  
Delta Clear to  
Delta Data Set  
Send (DCTS)  
Ready (DDSR)  
ADDR = 7  
ADDR = 0  
DLAB = 1  
ADDR = 1  
DLAB = 1  
Scratch Register (Note 4)  
Divisor Latch (LS)  
SCR  
DDL  
Bit 0  
Bit 0  
Bit 1  
Bit 1  
Divisor Latch (MS)  
DLM  
Bit 8  
Bit 9  
*DLAB is Bit 7 of the Line Control Register (ADDR = 3).  
Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.  
Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.  
Table 12 - Individual UART Channel Register Summary Continued  
BIT 2  
BIT 3  
BIT 4  
BIT 5  
BIT 6  
BIT 7  
Data Bit 2  
Data Bit 3  
Data Bit 4  
Data Bit 5  
Data Bit 6  
Data Bit 7  
Data Bit 2  
Data Bit 3  
Enable  
Data Bit 4  
0
Data Bit 5  
0
Data Bit 6  
0
Data Bit 7  
0
Enable  
Receiver Line MODEM  
Status  
Status  
Interrupt  
(ELSI)  
Interrupt  
(EMSI)  
SMSC DS – SP37E760  
Page 24  
Rev. 04/13/2001  
 复制成功!