REGISTER/SIGNAL
OUT2B
RTSB
DTRB
OUT1B
RESET CONTROL
RESET
RESET
RESET
RESET
RESET STATE
High
High
High
High
RCVR FIFO
XMIT FIFO
RESET/FCR1*FCR0/_FCR0
RESET/FCR1*FCR0/_FCR0
All bits low
All bits low
4.2 FIFO Interrupt Mode Operation
When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = “1”, IER bit 0 = “1”), RCVR interrupts occur as
follows:
1. The receive data available interrupt will be issued when the FIFO has reached its programmed trigger level; it is
cleared as soon as the FIFO drops below its programmed trigger level.
2. The IIR receive data available indication also occurs when the FIFO trigger level is reached. It is cleared when
the FIFO drops below the trigger level.
3. The receiver line status interrupt (IIR=06H), has higher priority than the received data available (IIR=04H)
interrupt.
4. The data ready bit (LSR bit 0)is set as soon as a character is transferred from the shift register to the RCVR
FIFO. It is reset when the FIFO is empty.
When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO time-out interrupts occur as follows:
1. A FIFO time-out interrupt occurs if all the following conditions exist:
at least one character is in the FIFO
The most recent serial character received was longer than 4 continuous character times ago. (If 2 stop bits
are programmed, the second one is included in this time delay.)
The most recent CPU read of the FIFO was longer than 4 continuous character times ago.
2. This will cause a maximum character received to interrupt issued delay of 160 msec at 300 BAUD with a 12 bit
character.
3. Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to
the baud rate).
4. When a time-out interrupt has occurred it is cleared and the timer reset when the CPU reads one character from
the RCVR FIFO.
5. When a time-out interrupt has not occurred the time-out timer is reset after a new character is received or after
the CPU reads the RCVR FIFO.
When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = “1”, IER bit 1 = “1”), XMIT interrupts occur
as follows:
1. The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as soon as the
transmitter holding register is written to (1 of 16 characters may be written to the XMIT FIFO while servicing this
interrupt) or the IIR is read.
2. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever the
following occurs: THRE=1 and there have not been at least two bytes at the same time in the transmit FIFO
since the last THRE=1. The transmitter interrupt after changing FCR0 will be immediate, if it is enabled.
Character time-out and RCVR FIFO trigger level interrupts have the same priority as the current received data
available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt.
4.3 FIFO Polled Mode Operation
With FCR bit 0 = “1” resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of operation.
Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled mode of operation.
In this mode, the user’s program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO
Polled Mode are as follows:
SMSC DS – SP37E760
Page 23
Rev. 04/13/2001
SMSC [ SMSC CORPORATION ]
