(1) = Compatible Mode
(3) = High Speed Mode
Note:
For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the
IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.09, Jan. 7, 1993. This document is
available from Microsoft.
5.1 IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES
5.1.1 DATA PORT
ADDRESS OFFSET = 00H
The Data Port is located at an offset of ‘00H’ from the base address. The data register is cleared at initialization by
RESET. During a WRITE operation, the Data Register latches the contents of the data bus with the rising edge of the
nIOW input. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports.
During a READ operation in SPP mode, PD0 - PD7 ports are buffered (not latched) and output to the host CPU.
5.1.2 STATUS PORT
ADDRESS OFFSET = 01H
The Status Port is located at an offset of ‘01H’ from the base address. The contents of this register are latched for
the duration of an nIOR read cycle. The bits of the Status Port are defined as follows:
5.1.2.1
BIT 0 TMOUT - TIME OUT
This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A logic “0”
means that no time out error has occurred; a logic “1” means that a time out error has been detected. This bit is
cleared by a RESET. Writing a one to this bit clears the time out status bit. On a write, this bit is self clearing and
does not require a write of a zero. Writing a zero to this bit has no effect.
BITS 1, 2 - are not implemented as register bits, during a read of the Printer Status Register these bits are a low level.
BIT 3 nERR - nERROR
The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic “0” means an error
has been detected; a logic “1” means no error has been detected.
5.1.2.1.1
BIT 4 SLCT - PRINTER SELECTED STATUS
The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic “1” means the printer
is on line; a logic “0” means it is not selected.
5.1.2.1.2
BIT 5 PE - PAPER END
The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic “1” indicates a paper end;
a logic “0” indicates the presence of paper.
5.1.2.2
BIT 6 nACK - nACKNOWLEDGE
The level on the nACK input is read by the CPU as bit 6 of the Printer Status Register. A logic 0 means that the
printer has received a character and can now accept another. A logic “1” means that it is still processing the last
character or has not received the data.
5.1.2.3
BIT 7 nBUSY - nBUSY
The complement of the level on the nBUSY input is read by the CPU as bit 7 of the Printer Status Register. A logic 0
in this bit means that the printer is busy and cannot accept a new character. A logic “1” means that it is ready to
accept the next character.
SMSC DS – SP37E760
Page 28
Rev. 04/13/2001
SMSC [ SMSC CORPORATION ]
