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SP37E760 参数 Datasheet PDF下载

SP37E760图片预览
型号: SP37E760
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3 V的I / O控制器的嵌入式应用 [3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS]
分类和应用: 控制器
文件页数/大小: 78 页 / 507 K
品牌: SMSC [ SMSC CORPORATION ]
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Error flag. Normally, the FIFO depth and the programmable trigger levels will give the CPU ample time to empty the  
Rx FIFO before an overrun occurs.  
One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data level in the  
FIFO. This could occur when data at the end of the block contains fewer bytes than the trigger level. No interrupt  
would be issued to the CPU and the data would remain in the UART. To prevent the software from having to  
check for this situation the chip incorporates a time-out interrupt.  
The time-out interrupt is activated when there is a least one byte in the Rx FIFO, and neither the CPU nor the Rx shift  
register has accessed the Rx FIFO within 4 character times of the last byte. The time-out interrupt is cleared or reset  
when the CPU reads the Rx FIFO or another character enters it.  
These FIFO related features allow optimization of  
CPU/UART transactions and are especially useful given  
the higher baud rate capability (256K baud).  
SMSC DS – SP37E760  
Page 26  
Rev. 04/13/2001  
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