Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Chapter 9 GPIO Runtime Registers
Table 9.1 shows the runtime registers summary in the GPIO logical Device. Table 9.2 shows the runtime
registers description in the GPIO logical device. These registers can only be accessed when LD_NUM bit
in the TEST 7 configuration register is ‘0’ (see Table 11.3). The register offsets are from the base address
programmed in the GPIO logical device.
Table 9.1 – GPIO Runtime Registers Summary, LD_NUM = 0
REGISTER
OFFSET
(hex)
TYPE
PCI Reset
VCC POR VTR POR
SOFT
REGISTER
RESET
00
01
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x04
0x04
0x04
0x04
0x05
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GP10
GP11
GP12
GP13
GP14
GP15
GP16
GP17
GP20
GP21
GP22
GP23
02
03
04
05
06
07
08
09
0A
0B
0C
0D-14
15
GP24
Reserved – reads return 0
GP1
GP2
R/W
R/W
R
0x00
0x00
-
16
17-1F
Reserved – reads return 0
SMSC LPC47M182
161
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
DATASHEET
SMSC [ SMSC CORPORATION ]
