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LPC47M182-NR 参数 Datasheet PDF下载

LPC47M182-NR图片预览
型号: LPC47M182-NR
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的I / O控制器,主板胶合逻辑 [ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC]
分类和应用: 控制器
文件页数/大小: 223 页 / 1215 K
品牌: SMSC [ SMSC CORPORATION ]
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Advanced I/O Controller with Motherboard GLUE Logic  
Datasheet  
REG OFFSET  
NAME  
PME_EN2  
DESCRIPTION  
PME Wake Enable Register 2  
(Type)  
0x0D  
This register is used to enable individual LPC47M182  
PME wake sources onto the nIO_PME wake bus.  
When the PME Wake Enable register bit for a wake  
source is active (“1”), if the source asserts a wake event  
so that the associated status bit is “1” and the PME_En  
bit is “1”, the source will assert the nIO_PME signal.  
When the PME Wake Enable register bit for a wake  
source is inactive (“0”), the PME Wake Status register  
will indicate the state of the wake source but will not  
assert the nIO_PME signal.  
Default = 0x00  
on VTR POR  
(R/W)  
Bit[0] GP10  
Bit[1] GP11  
Bit[2] GP12  
Bit[3] GP13  
Bit[4] GP14  
Bit[5] GP15  
Bit[6] GP16  
Bit[7] GP17  
The PME Wake Enable register is not affected by Vcc  
POR, SOFT RESET or HARD RESET.  
PME Wake Enable Register 1  
PME_EN1  
0x0E  
This register is used to enable individual PME wake  
sources onto the nIO_PME wake bus.  
When the PME Wake Enable register bit for a wake  
source is active (“1”), if the source asserts a wake event  
so that the associated status bit is “1” and the PME_En  
bit is “1”, the source will assert the nIO_PME signal.  
When the PME Wake Enable register bit for a wake  
source is inactive (“0”), the PME Wake Status register  
will indicate the state of the wake source but will not  
assert the nIO_PME signal.  
Default = 0x00  
on VTR POR  
(R/W)  
Bit[0] Reserved (Note 1)  
Bit[1] RI2  
Bit[2] RI1  
Bit[3] KBD  
Bit[4] MOUSE  
Bit[5] SPEKEY (Wake on specific key)  
Bit[6] FAN_TACH1  
Bit[7] FAN_TACH2  
The PME Wake Enable register is not affected by Vcc  
POR, SOFT RESET or HARD RESET.  
Bits[7:0] Reserved – reads return 0  
N/A  
0x0F  
(R)  
0x10  
LED  
LED Register  
Default = 0x03 on  
VTR POR  
(R/W)  
Bit[0] GRN_YLW  
0 = Select YLW_LED if nSLP_S5 if high  
1 = Select GRN_LED if nSLP_S5 is high  
Bit[1] SDY_BLK  
0 = Blink at 0.67 Hz with 39.6% duty cycle  
(0.59375 sec high, 0.90625 low) if nSLP_S5 is  
high  
1 = Steady if nSLP_S5 is high  
Bit[7:2] Reserved  
SMSC LPC47M182  
157  
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)  
DATASHEET  
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