Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table 7.33 – VGA DDCSCL Voltage Translation Logic
DDC Vs. GPIO
ALTERNATE
FUNCTION SELECT
BIT/S
GPIO/EETI/Reserved
DDC (DEFAULT)
DDC (DEFAULT)
DDCSCL_3V
Don’t Care
DDCSCL_5V
Don’t Care
CURRENT ACROSS THE SWITCH
No Current flow (0 mA)
Current flows from DDCSCL_5V or
0V
0V
DDCSCL_3V
3.6V (max)
5.5V (max)
No Current flow (0 mA)
VCC5V
VCC
LPC47M182
2.2k
4.7k
4.7k
2.2k
25ohm
Max
DDCSDA_3V
DDCSDA_5V
DDCSCL_5V
SEE NOTE
VGA
MCH
25ohm
Max
Connector
DDCSCL_3V
EN
6.2V
6.2V
GPIO Alternate
Function
Select bit
NOTE: The switch is implemented as an n-channel switch that will not pass a full voltage swing.
It provides a current path to ground.
The board designer should treat each signal pair to the switch as a separate bus with a
resistance in the path.
The maximum resistance of the switch between any bus to any other bus is 25ohms (when the
switch is on). When the switch is off the impedance is Hi-Z and the current is zero.
The design requires pull-ups on each of the busses shown above.
It is recommended that the pullups be selected so that the total maximum current on both
busses does not exceed 2mA to limit the voltage drop across the switch.
Figure 7.10 – VGA DDC Voltage Translation Circuit
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
142
SMSC LPC47M182
DATASHEET
SMSC [ SMSC CORPORATION ]
