Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table 7.27 – nIDE_RSTDRV Pin
POWER
BUFFER
NAME
DESCRIPTION
WELL
nIDE_RSTDRV
OD8
VCC
IDE Reset Output
Table 7.28 – nIDE_RSTDRV Truth Table
nPCI_RESET (Input) nIDE_RSTDRV (Output)
0
0
1
Hi-Z
See Table 13.1 for nIDE_RSTDRV timing.
7.33 PCI Reset Output Pins
The nPCIRST_OUT is 3.3V buffered copy of nPCI_RESET. The nPCIRST_OUT2 is 3.3V buffered copy of
nPCI_RESET.
The nPCIRST_OUT and nPCIRST_OUT2 signals will be low when VCC=0.
Table 7.29 – nPCIRST_OUT Pins
POWER
NAME
BUFFER
DESCRIPTION
WELL
VTR
nPCIRST_OUT
nPCIRST_OUT2
OP14
OP14
Buffered PCI Reset Output
Buffered PCI Reset Output
VTR
Table 7.30 – nPCIRST_OUT and nPCIRST_OUT2 Truth Table
INPUT
nPCI_RESET
OUTPUTS
nPCIRST_OUT2
nPCIRST_OUT
0
1
0
1
0
1
See Table 13.2 for nPCI_RSTOUT and nPCI_RSTOUT2 timings.
7.34 Voltage Translation Circuit
Table 7.31 – Voltage Translation DDC Pins
POWER
NAME
BUFFER
DESCRIPTION
WELL
VTR
DDCSDA_5V/ GP20
IO_SW
5V DDC Data IOD/ GPIO
(Note)
DDCSCL_5V/ GP21
DDCSDA_3V/ GP22
IO_SW
IO_SW
VTR
VTR
5V DDC Clock IOD/ GPIO
(Note )
3.3V DDC Data IOD/ GPIO
(Note)
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
140
SMSC LPC47M182
DATASHEET
SMSC [ SMSC CORPORATION ]
