Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
7.27.4 GPIO Operation
The operation of the GPIO ports is illustrated in Figure 7.4.
GPIO
GPIO
Configuration
Register bit-1
(Polarity)
Configuration
Register bit-0
(Input/Output)
D-TYPE
SD-bit
D
Q
GPx_nIOW
GPx_nIOR
GPIO
PIN
Transparen
t
0
1
Q
D
GPIO
Data Register
Bit-n
Figure 7.4 – GPIO Function Illustration
Note:
Figure 7.4 is for illustration purposes only and is not intended to suggest specific implementation details.
When a GPIO port is programmed as an input, reading it through the GPIO data register latches either the
inverted or non-inverted logic value present at the GPIO pin. Writing to a GPIO port that is programmed
as an input has no effect (Table 7.19)
When a GPIO port is programmed as an output, the logic value or the inverted logic value that has been
written into the GPIO data register is output to the GPIO pin. Reading from a GPIO port that is
programmed as an output returns the last value written to the data register (Table 7.19). When the GPIO
is programmed as an output, the pin is excluded from the PME logic.
Table 7.19 – GPIO Read/Write Behavior
HOST OPERATION
READ
GPIO INPUT PORT
LATCHED VALUE OF GPIO PIN
NO EFFECT
GPIO OUTPUT PORT
LAST WRITE TO GPIO DATA REGISTER
BIT PLACED IN GPIO DATA REGISTER
WRITE
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
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SMSC LPC47M182
DATASHEET
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