Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
If either of the isolation bits (M_ISO, K_SIO) is set prior to entering a sleep state where VCC goes inactive
(S3-S5), then the 8042 must be reset upon exiting the sleep mode. Write 0x40 to global configuration
register 0x2C to reset the 8042. The 8042 must then be taken out of reset by writing 0x00 to register 0x2C
since the bit that resets the 8042 is not self-clearing. Caution: Bit 6 of configuration register 0x2C is used
to put the 8042 into reset - do not set any of the other bits in register 0x2C, as this may produce undesired
results.
It is not necessary to reset the 8042 if the isolation bits are used for a sleep state where VCC does not go
inactive (S1, S2).
Note:
It not necessary to reset the 8042 when ISO_MODE bit is set to ‘0’, and M_ISO and K_ISO isolation bit are
not set. This is because nLPCPD goes inactive high (it will remove isolation of the signals when system
sleep state is exited) prior to nPCI_RESET going inactive high. The nPCI_RESET going inactive high
resets the 8042.
User Note Regarding External Keyboard and Mouse:
This is an application matter resulting from the behavior of the external 8042 in the keyboard.
When the external keyboard and external mouse are powered up, the KDAT and MDAT lines are driven
low. This sets the KBD bit (D3) and the MOUSE bit (D4) of the PME Wake Status Register since the
KDAT and MDAT signals cannot be isolated internal to the part. This causes an nIO_PME to be generated
if the keyboard and/or mouse PME events are enabled. Note that the keyboard and mouse isolation
modes only prevent the internal 8042 in the part from setting these status bits.
Case 1: Keyboard and/or Mouse Powered by VTR
The KBD and/or MOUSE status bits will be set upon a VTR POR if the keyboard and/or mouse are
powered by VTR. In this case, an nIO_PME will not be generated, since the keyboard and mouse PME
enable bits are reset to zero on a VTR POR. The BIOS software needs to clear these PME status bits after
power-up.
Case 2: Keyboard and/or Mouse Powered by VCC
The KBD and/or MOUSE status bits will be set upon a VCC POR if the keyboard and/or mouse are
powered by VCC. In this case, an nIO_PME will be generated if the enable bits were set for wakeup,
since the keyboard and mouse PME enable bits are VTR powered. Therefore, if the keyboard and mouse
are powered by VCC, the enable bits for keyboard and mouse events should be cleared prior to entering a
sleep state where VCC is removed (i.e., S3) to prevent a false PME from being generated. In this case, the
keyboard and mouse should only be used as PME and/or wake events from the S0 and/or S1 states. The
BIOS software needs to clear these PME status bits after power-up.
7.27 General Purpose I/O
The LPC47M182 provides a set of flexible Input/Output control functions to the system designer through
the 13 independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform basic
I/O and can be individually enabled to generate a PME (except GP24). GPIOs must be programmed as
inputs to generate a PME.
7.27.1 GPIO Pins
The Table 7.16 summarizes the GPIO functionality, including PME, Either Edge Triggered Interrupt (EETI)
input capability and the power source for the buffer on the I/O pads.
SMSC LPC47M182
127
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
DATASHEET
SMSC [ SMSC CORPORATION ]
