edge. If the EETI function is selected for a GPIO then both a high-to-low and a low-to-high edge will set the
corresponding PME status bits. Status bits are cleared on a write of ‘1’.
The PME Wake registers also include status and enable bits for the fan tachometer input.
See the “Keyboard and Mouse PME Generation” section for information about using the keyboard and mouse signals
to generate a PME.
The P12 and P16 bits enable a PME event on single high-to-low edge or on both high-to-low and low-to-high edges.
Default is single edge. There is also a polarity select bit in the configuration register at 0xF0 in logical device 7. The
register that selects the edge, Edge Select register, is located at the address programmed in the Base I/O Address
register in the Logical Device A at an offset of 21h. Refer also to PME Status and Enable register 9. See the
Runtime Registers sections for description on these registers.
If both edges are selected for generating a PME via P12 and P16, then the PME is generated on each edge until the
corresponding PME status bit is cleared.
Note that P12 and P16 status bits are cleared on by write of ‘1’. The SMI generated by P12 and P16 is deasserted
when the associated PME status bit is cleared.
In the LPC47S45x the IO_PME# pin can be programmed to be an open drain, active low, driver. The LPC47S45x
IO_PME# pin is fully isolated from other external devices that might pull the IO_PME# signal low; i.e., the IO_PME#
signal is capable of being driven high externally by another active device or pull-up even when the LPC47S45x Vcc is
grounded, providing VTR power is active. The LPC47S45x IO_PME# driver sinks 6mA at .55V max (see section
4.2.1.1 DC Specifications, page 122, in the PCI Local Bus Specification, Revision 2.1).
The PME registers are run-time registers as follows. These registers are located in system I/O space at an offset
from Runtime Registers Block, the address programmed in Logical Device A at registers 0x60 and 0x61.
The following registers are for GPIO wakeup events:
PME Wake Status 2 (PME_STS2), PME Wake Enable 2 (PME_EN2)
PME Wake Status 3 (PME_STS3), PME Wake Enable 3 (PME_EN3)
PME Wake Status 4 (PME_STS4), PME Wake Enable 4 (PME_EN4)
PME Wake Status 5 (PME_STS5), PME Wake Enable 5 (PME_EN5)
PME Wake Status 7 (PME_STS7), PME Wake Enable 7 (PME_EN7)
The PME Wake Status 6 (PME_STS6), PME Wake Enable 6 (PME_EN6) registers are for the device interrupt PME
events.
The PME Wake Status 1 (PME_STS1), PME Wake Enable 1 (PME_EN1) registers are for pin and internal function
PME events.
See PME register description in the Runtime Register Section.
7.4.1 ‘WAKE ON SPECIFIC KEY’ OPTION
The LPC47S45x has logic to detect a single keyboard scan code for wakeup (PME generation). The scan code is
programmed onto the Keyboard Scan Code Register, a runtime register at offset 0x5F from the base address located
in the primary base I/O address in Logical Device A. This register is powered by VTR and reset on VTR POR.
The PME status bit for this event is located in the PME_STS1 register at bit 5 and the PME enable bit for this event is
located in the PME_EN1 register at bit 5. See the Runtime Register section for a definition of these registers.
Data transmissions from the keyboard consist of an 11-bit serial data stream. A logic 1 is sent at an active high level.
The following table shows the functions of the bits.
BIT
FUNCTION
Start bit (always 0)
1
2
3
4
5
Data bit 0 (least significant bit)
Data bit 1
Data bit 2
Data bit 3
SMSC LPC47S45x
Page 152 of 259
Rev. 06-01-06
DATASHEET
SMSC [ SMSC CORPORATION ]
