7.3.3 RTC ALARM AS A PME EVENT
The ACPI specification requires that the RTC alarm generate a hardware wake-up event from the sleeping state. For
a description of the RTC alarm, see section 6.9 Real Time Clock – General Description on page 97.
The RTC alarm may be enabled by the RTC_EN bit in the PM1 Enable Register. If enabled, an RTC alarm event will
generate a signal into the wake-up logic to activate the nPS_ON signal and will set the RTC_STS bit in the PM1_STS
register. If the SCI_EN bit is set, the enabled RTC alarm will generate a PME event.
Note: If the SCI_EN bit is not set and the SMI_SCI_ENB bit is set to ‘0’ and the EN_SMI bit is set to ‘1’ in the
SMI_EN2 register, then an SMI will be generated for the enabled RTC event.
Note: The RTC Alarm is not an option in the PME registers, it can only generate a PME event if enabled in the Power
Management 1 Enable Register 2 (PM1_EN2). It does NOT require that the PME Enable bit in the PME_EN register
be set in order to generate an nIO_PME.
The RTC Alarm is equipped with an Alarm Remember Enable bit (AL_REM_EN) in the PS_CNTRL registers, Logical
Device A at 0xF8. If the alarm is set to wake the system during a period of time in which VTR=0 and the
AL_REM_EN bit is set, then when VTR power is restored to the system the alarm will be activated and thereby wake
the system.
7.4 PME Support
The LPC47S45x offers support for power management events (PMEs). PME events can be generated from the
PME, status and enable, registers or by the PM1 and GPE registers implemented to support System Control Interrupt
(SCI) events in an ACPI system. A power management event is indicated to the chipset via the assertion of the
IO_PME# signal. In the LPC47S45x, the IO_PME# is asserted by:
Active transitions on the ring indicator inputs nRI1 and nRI2
Active keyboard-data edges
Active mouse-data edges
Wakeup on Specific key
Super I/O Device Interrupts
Watchdog Timer
Programmable edges on GPIO pins
Fan tachometer event
RTC alarm event
Power Button event
The GP42/nIO_PME pin, when selected for the nIO_PME function, can be programmed to be active high or active
low via the polarity bit in the GP42 register. The output buffer type of the pin can be programmed to be open-drain or
push-pull via bit 7 of the GP42 register. The nIO_PME pin function defaults to active low, open-drain output.
PME functionality is controlled by the PME status and enable registers in the runtime registers block, which is located
at the address programmed in configuration registers 0x60 and 0x61 in Logical Device A. The PME Enable bit,
PME_EN, globally controls PME Wake-up events. When PME_EN is inactive, the IO_PME# signal can not be
asserted by events in the PME_STS registers. When PME_EN is asserted, any wake source whose individual PME
Wake Enable register bit is asserted can cause IO_PME# to become asserted.
The PME Status register indicates that an enabled wake source has occurred and if the PME_EN bit is set, asserts
the IO_PME# signal. The PME Status bit is asserted by active transitions of PME wake sources. PME_STS will
become asserted independent of the state of the global PME enable, PME_EN.
The following pertains to the PME status bits for each event:
The output of the status bit for each event is combined with the corresponding enable bit to set the PME status
bit.
The status bit for any pending events must be cleared in order to clear the PME_STS bit. Status bit are cleared
on a write of ‘1’.
For the GPIO events, the polarity of the edge used to set the status bit and generate a PME is controlled by the
polarity bit of the GPIO control register. For non-inverted polarity (default) the status bit is set on the low-to-high
SMSC LPC47S45x
Page 151 of 259
Rev. 06-01-06
DATASHEET
SMSC [ SMSC CORPORATION ]
