7.3 ACPI Features
These features comply with the ACPI Specification, Revision 1.0b.
7.3.1 LEGACY/ACPI SELECT
The LPC47S45x supports both legacy operating systems and ACPI systems. System software for legacy power
management consists of an SMI interrupt handler while for ACPI it consists of the ACPI driver (SCI interrupt handler).
Therefore, the LPC47S45x offers both SMI specific registers (i.e., SMI_ENx & SMI_STSx) and it offers ACPI specific
registers, referred to as PM1 and GPE1 registers. If SCI generation is enabled then all power management events
enabled in the PM1 and GPE registers will generate an IO_PME# and initiate the wake-up logic on the chip. It is also
possible to enable the SCI registers to generate an SMI signal.
Note: Any enable event in the PM1 and GPE1 registers will always generate a signal into the wake-up logic.
Therefore, the following options have been made available for both legacy and ACPI systems. See section 7.2 ACPI
Specific Registers on page 148 for a description of how to implement the ACPI specific registers.
The LPC47S45x offers three options for the SMI/SCI select capability:
1. SMI only
-
Enable SMI registers to generate an IO_SMI# events only.
2. SMI with wakeup
-
Enable PM1 and GPE registers to generate an IO_SMI# and a wakeup event
3. SCI Select
-
Enable PM1 and GPE registers to generate an IO_PME# and initiate wake-up (i.e., IO_SMI# signal not
generated). SCI events are also referred to as PME events
Note: Only events enabled in the PM1 or GPE registers can set a status bit to initiate a signal directly into the
wakeup logic on the LPC47S45x. Events enabled in the SMI registers can only generate an IO_SMI# signal, they
can never generate a signal to initiate wakeup directly.
Note: The PME events generated by the PM1 and GPE1 registers have no effect on the PME events in the
PME_EN and PME_STS registers.
Note: Wake-up events in the PM1 and GPE registers cannot initiate a wakeup event after a power button override
has occurred.
7.3.2 POWER BUTTON WITH OVERRIDE
The power button switches the system from the sleeping/soft off state to the working state, and signals the OS to
transition to a soft off state from the working state.
The power button has status and enable bits in the PM1 status and enable registers. When the power button is
pressed for less than four seconds it will always set the PWRBTN_STS bit on the button press (high-to-low) edge. If
nPS_ON is inactive, it will generate a signal into the wakeup logic to assert the nPS_ON signal active low. (Note:
When nPS_ON is pulled low, the power supply is turned on and VCC goes to 3.3V.) If the PWRBTN_EN bit is set, a
PME, SCI or SMI may also be generated depending on the state of the PME_EN bit in the PME Enable register, the
SCI_EN bit in the PM1_CNTRL1 register and the SMI_SCI_ENB bit in the PS_CNTRL register.
If the power button is held for more than four seconds when VCC is active, a power button override will be initiated
and VCC will be shut off. Once a power button override occurs, only a power button press (an active nPB_IN signal)
can wake the system.
The power button override event, as required by the ACPI specification, will transition the system to the soft-off state.
The PM1 status register has a bit, called PWRBTNOR_STS that gets set to indicate an override event has occurred.
This event clears the PWRBTN_STS bit. This override event is described as follows: If the user presses the power
button for more than 4 seconds while the system is in the working state, a hardware event is generated and the
system will transition to the soft off state.
Note: The power buttonalways results in a wake-up event (if nPS_ON is inactive), regardless of the setting of
PWRBTN_EN.
Note: The LPC47S45x may also be powered down by software writing a ‘1’ to the PSOFF bit located in the Power
Supply Control Register (PS_CNTRL).
SMSC LPC47S45x
Page 150 of 259
Rev. 06-01-06
DATASHEET
SMSC [ SMSC CORPORATION ]
