8
RUNTIME REGISTERS
8.1 Runtime Registers Block Summary
The following registers are runtime registers in the LPC47S45x. They are located at the address programmed in the
Base I/O Address in Logical Device A (Runtime Registers Block) at the offset shown. These registers are powered
by VTR.
Table 79. Runtime Register Block Summary
SMBus2
Vbat
POR
OFFSET
(hex)
PCI
RESET
VCC
POR
VTR
POR
SOFT
TYPE
REGISTER
REG
RESET
OFFSET
00
01
02
03
04
05
06
07
08
09
R/W
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0x00
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PME_STS
-
-
-
-
-
-
-
-
-
-
Reserved
R/W
R
0x00
-
PME_EN
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x01
(Note 6)
0x00
0x00
0x00
0x00
0x00
0x00
0x00
(Note 6)
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
PME_STS1
PME_STS2
PME_STS3
PME_STS4
PME_STS5
(Note 6) (Note 6)
(Note 6) (Note 6) PME_STS6
0A
0B
0C
0D
0E
0F
10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PME_EN1
PME_EN2
PME_EN3
PME_EN4
PME_EN5
PME_EN6
-
-
-
-
-
-
-
(Note 6) (Note 6)
(Note 6) (Note 6) SMI_STS 1
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SMI_STS 2
SMI_STS3
SMI_STS4
SMI_STS5
SMI_STS6
SMI_EN1
SMI_EN2
SMI_EN3
SMI_EN4
SMI_EN5
SMI_EN6
MSC_STS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0x00
0x00
UART2 FIFO Control
Shadow
1E
1F
R/W
R
0x03
0x02
0x03
0x02
-
-
-
-
-
Force Disk Change
-
-
0x02
Floppy Data Rate Select
Shadow
20
21
R
0x00
-
0x00
-
0x00
0x00
-
-
-
-
UART1 FIFO Control
Shadow
-
-
R/W
Edge Select Register
SMSC LPC47S45x
Page 156 of 259
Rev. 06-01-06
DATASHEET
SMSC [ SMSC CORPORATION ]
