BIT
FUNCTION
6
Data bit 4
Data bit 5
Data bit 6
7
8
9
Data bit 7 (most significant bit)
Parity bit (odd parity)
10
11
Stop Bit (always 1)
The timing for the keyboard clock and data signals are shown in the “Timing Diagrams” section.
The process to find a match for the scan code stored in the Keyboard Scan Code register is as follows:
Begin sampling the data at the first falling edge of the keyboard clock following a period where the clock line has
been high for 115-145usec. The data at this first clock edge is the start bit. The first data bit follows the start bit (clock
2). Sample the data on each falling edge of the clock. Store the eight bits following the stop bit to compare with the
scan code stored in the Keyboard Scan Code register. Sample the comparator within 100usec of the falling edge of
clock 9 (for example, at clock 10).
Sample the parity bit and check that the 8 data bits plus the parity bit always have an odd number of 1’s (odd parity).
The process repeats until a match is found. If the 8 data bits match the scan code stored in the Keyboard Scan Code
register and the parity is correct, then it is considered a match. When a match is found and if the stop bit is 1, set the
event status bit (bit 5 of the PME_STS1 register) to ‘1’ within 100usec of the falling edge of clock 10.
The state machine will reset after 11 clocks and the process will restart. The process will continue until it is shut off by
setting the SPEKEY_EN bit (see following sub-section).
The state machine will reset if there is a period where the clock remains high for more than one keyboard clock
period (115-145usec) in the middle of the transmission (i.e., before clock 11). This is to prevent the generation of a
false PME.
The CLK32_PRSN bit (bit 0 of the CLOCKI32 register at 0xF0 in Logical Device A) will determine the clock source for
this feature when the part is powered by VCC. If an external 32kHz clock source is not connected, the 32kHz internal
signal is derived from the 14MHz clock when VCC is active. Use the 32kHz clock input or crystal oscillator for this
feature when the part is under trickle power. This feature will not work when the part is under trickle power (VCC
removed) if an external 32kHz clock source is not connected.
The SPEKEY_EN bit at bit 1 of the CLOCKI32 register at 0xF0 in Logical Device A is used to control this feature.
This bit is used to turn the logic for this feature on and off. It will disable the 32kHz clock input to the logic. The logic
will draw no power when disabled. The bit is defined as follows:
0= “Wake on specific key” logic is on (default)
1= “Wake on specific key” logic is off
Note: The generation of a PME for this event is controlled by the PME enable bit (located in the PME_EN1 register at
bit 5) when the logic for feature is turned on.
SMSC LPC47S45x
Page 153 of 259
Rev. 06-01-06
DATASHEET
SMSC [ SMSC CORPORATION ]
