If the SMBus Slave Interface receives an invalid Register Address after acknowledging a valid slave address and a
write field bit, it will follow through with the command protocol (if the command protocol from the master is correct). It
will latch the register address and ACK. In the case of a read byte command, it will ACK the second START, slave
address and read field, but return zero data. In the case of a write byte command, it will ACK the register data but it
will have no effect. If the command protocol from the master is not correct, it will respond as described below.
Slave Receives Multiple Byte Read Command Protocol
This condition pertains to an attempt by the host to transfer two or more bytes in a read command. If the SMBus
Slave Interface receives an ACK after the first register data byte it will stop responding and return to idle.
Note: This pertains to an attempted autoincrement read as in I2C. The LPC47S45x does not support the SMBus
block read command.
Slave Receives Multiple Byte Write Command Protocol
This condition pertains to an attempt by the host to transfer two or more bytes in a write command. If the SMBus
Slave Interface receives a second data byte following the register data byte ACK, it will stop responding (NACK) and
return to the idle state. Note: This pertains to an attempted autoincrement write as in I2C. The LPC47S45x does not
support the SMBus block write command and if a byte count is given in the data byte field, it will be interpreted as
data.
Improper Field Within Command Protocol
If the SMBus slave interface receives an improper field, it will stop responding and return to the idle state. Several
cases follow. Note that by not responding, a NACK will be produced in the ACK/NACK field that follows the improper
field.
Stop Flag Received During Command/Data Expectation
If the SMBus Slave Interface receives a STOP where it is not expected, it will not respond and return to idle.
Start Sequence Received in Middle of Transaction
If the SMBus Slave Interface receives a correct start sequence (start bit, valid slave address and write bit) in the
middle of a transaction (not a read byte transaction) it will stop responding and return to idle.
Read Field Received Following the First Slave Address
If the SMBus Slave Interface receives a read bit following the first slave address (excluding the bit field following the
second slave address of a read command), it will not respond and then return to idle.
Write Field Received Following the Second Slave Address of a Read Command
If the SMBus Slave Interface receives a write bit following the second slave address of a read command, it will not
respond and then return to idle.
6.18.7 SLAVE DEVICE TIME-OUT
The SMBus2 slave device will always time-out when SCLK is held low longer than TTIME-OUT Max = 35ms. The
SMBus Slave Interface resets and returns to idle if SCLK is held low for longer than TTIME-OUT Max.
6.18.8 STRETCHING THE SCLK SIGNAL
The LPC47S45x supports stretching of the SCLK low time between byte transfers (byte+ACK). The SMBus2 slave
device will not hold the SCLK low longer than ten CLOCKI pulses.
6.18.9 SMBUS TIMING
The SMBus Slave Interface complies with the SMBus AC Timing Specification. See FIGURE 37 in the Timing
Diagrams section.
6.18.10 BUS RESET SEQUENCE
The SMBus Slave Interface will reset and return to the idle state upon a START field followed immediately by a STOP
field.
SMSC LPC47S45x
Page 142 of 259
Rev. 06-01-06
DATASHEET
SMSC [ SMSC CORPORATION ]
