SMBus2
NAME
DESCRIPTION
REG OFFSET
(hex)
Bit[5] Serial Port 2 Enable
0=No effect: UART2 controlled by its activate bit;
1=UART2 Disabled
Bit[6] Serial Port 1 Enable.
0=No effect: UART1 controlled by its activate bit;
1=UART1 Disabled
Bit[7] Parallel Port Enable.
0=No effect: PP controlled by its activate bit;
1=PP Disabled
Note: If “0” (enabled), bits[7:3] have no effect on the devices; devices
are controlled by their respective activate bits. If “1” (disabled),
bits[7:3] override the activate bits in the configuration registers for
each logical block.
Note: Any peripheral that is disabled in this register will not be accessible by either the LPC interface or the SMBus.
See the LPC Device Disable Register in the Runtime Register section.
SMBus2, SMB_ARB Arbitration Register
This register is used to request access to the X-Bus through Bit[0]. If the request is granted, Bit[1] will be set to ‘1’ by
the hardware. The host/master should monitor this bit to know when to initiate an I/O cycle. If the the LPC interface
locks up or cannot remove its request, an SMBus master request is available on Bit[3]. If this bit is asserted, any
active LPC transactions are immediately terminated.
Table 75 − SMBus2, SMB_ARB Arbitration Register
SMBus2
NAME
SMB_ARB
REG OFFSET
(hex)
DESCRIPTION
02
Bit [0] = SMB_REQ, SMBus2 X-Bus Access Request
Bit [1] = SMB_GNT, SMBus2 X-Bus Access Grant
Arbitration Register
Bit 0 and Bit 2 Bit [2] = SMB_MREQ SMBus2 X-Bus Master Request
are R/W by the
SMBus2,
Default = 0x00
Bit [3] = Reserved
Bit [4] = Reserved
Bit [5] = Reserved
Bit [6] = Reserved
Bit [7] = Reserved
on VCC POR and
PCI Reset.
Bit 1 is set/reset
by
the
arbitration logic,
and Read only
by the SMBus2.
Note: Since both the LPC Bus and SMBus are able to access the X-Bus, arbitration registers have been provided. It
is important to note that when XMB_MREQ=1, accesses to the X-Bus by the SMBus will take precedence over
accesses made by the LPC Bus. That means any transaction initiated by the LPC bus will be immediately
terminated.
6.18.6 INVALID COMMAND PROTOCOL RESPONSE BEHAVIOR
The LPC47S45x registers that are accessed with an invalid command protocol will not be updated. A register will
only be updated following a valid command protocol. The only valid commands are the read byte and write byte
commands described in section 6.18.1 SMBus Protocols supported by SMBus2.
Invalid Slave Address
If the host sends an invalid slave address, the SMBus2 interface will not respond and it will return to its idle state
Invalid Register Address
SMSC LPC47S45x
Page 141 of 259
Rev. 06-01-06
DATASHEET
SMSC [ SMSC CORPORATION ]
