Once all IRQ/Data Frames have completed the Host Controller will terminate SER_IRQ activity by initiating a Stop
Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is indicated when the SER_IRQ is low
for two or three clocks. If the Stop Frame’s low time is two clocks then the next SER_IRQ Cycle’s sampled mode is
the Quiet mode; and any SER_IRQ device may initiate a Start Frame in the second clock or more after the rising
edge of the Stop Frame’s pulse. If the Stop Frame’s low time is three clocks then the next SER_IRQ Cycle’s sampled
mode is the Continuos mode; and only the Host Controller may initiate a Start Frame in the second clock or more
after the rising edge of the Stop Frame’s pulse.
Latency
Latency for IRQ/Data updates over the SER_IRQ bus in bridge-less systems with the minimum Host supported
IRQ/Data Frames of seventeen, will range up to 96 clocks (3.84μS with a 25MHz PCI Bus or 2.88uS with a 33MHz
PCI Bus). If one or more PCI to PCI Bridge is added to a system, the latency for IRQ/Data updates from the
secondary or tertiary buses will be a few clocks longer for synchronous buses, and approximately double for
asynchronous buses.
EOI/ISR Read Latency
Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could cause an
EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a system fault. The host
interrupt controller is responsible for ensuring that these latency issues are mitigated. The recommended solution is
to delay EOIs and ISR Reads to the interrupt controller by the same amount as the SER_IRQ Cycle latency in order
to ensure that these events do not occur out of order.
AC/DC Specification Issue
All SER_IRQ agents must drive / sample SER_IRQ synchronously related to the rising edge of PCI bus clock.
SER_IRQ pin uses the electrical specification of PCI bus. Electrical parameters will follow PCI spec. section 4,
sustained tri-state.
Reset and Initialization
The SER_IRQ bus uses PCI_RESET# as its reset signal. The SER_IRQ pin is tri-stated by all agents while
PCI_RESET# is active. With reset, SER_IRQ Slaves are put into the (continuous) IDLE mode. The Host Controller is
responsible for starting the initial SER_IRQ Cycle to collect system’s IRQ/Data default values. The system then
follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for subsequent SER_IRQ Cycles. It is
Host Controller’s responsibility to provide the default values to 8259’s and other system logic before the first
SER_IRQ Cycle is performed. For SER_IRQ system suspend, insertion, or removal application, the Host controller
should be programmed into Continuous (IDLE) mode first. This is to guarantee SER_IRQ bus is in IDLE state before
the system configuration changes.
6.10.2 ROUTABLE IRQ TO SERIAL IRQ CONVERSION CAPABILITY
IRQINx functions are on pins 61 (IRQINA), 62 (IRQINB), 40 (IRQINC) and 44 (IRQIND) and are muxed onto the
GPIO pins as inputs. The IRQINx pin’s IRQ time slot in the Serial IRQ stream is selected via a 4-bit control register
for each IRQINx function. A value of 0000 disables the IRQ function. These pins are implemented such that internal
functions take precedence over the IRQIN pins, i.e. if the IRQIN control register is set to 0x06 and the internal floppy
is set to 0x06, the floppy alone will drive the Serial IRQ stream in the IRQ6 time slot. See Configuration registers
located at an offset 0xF4 and 0xF5 in Logical Device A.
User Note: In order to use an IRQ for one of the IRQINx inputs that are muxed on the GPIO pins, the corresponding
IRQ must not be used for any of the devices in the LPC47S45x.
SMSC DS – LPC47S45x
Page 107 of 259
Rev. 07/09/2001
DATASHEET
SMSC [ SMSC CORPORATION ]
