欢迎访问ic37.com |
会员登录 免费注册
发布采购

LPC47S45X 参数 Datasheet PDF下载

LPC47S45X图片预览
型号: LPC47S45X
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的I / O与X -Bus接口 [Advanced I/O with X-Bus Interface]
分类和应用:
文件页数/大小: 259 页 / 1575 K
品牌: SMSC [ SMSC CORPORATION ]
 浏览型号LPC47S45X的Datasheet PDF文件第107页浏览型号LPC47S45X的Datasheet PDF文件第108页浏览型号LPC47S45X的Datasheet PDF文件第109页浏览型号LPC47S45X的Datasheet PDF文件第110页浏览型号LPC47S45X的Datasheet PDF文件第112页浏览型号LPC47S45X的Datasheet PDF文件第113页浏览型号LPC47S45X的Datasheet PDF文件第114页浏览型号LPC47S45X的Datasheet PDF文件第115页  
reads the input data register (DBB), this bit is automatically reset and the interrupt is cleared. There is no  
output pin associated with this internal signal.  
OBF  
(Output Buffer Full) - This flag is set to whenever the LPC47S45x CPU write to the output data register (DBB).  
When the host system reads the output data register, this bit is automatically reset.  
6.11.7 EXTERNAL CLOCK SIGNAL  
The LPC47S45x Keyboard Controller clock source is a 12 MHz clock generated from a 14.318 MHz clock. The reset  
pulse must last for at least 24 16 MHz clock periods. The pulse-width requirement applies to both internally (Vcc POR)  
and externally generated reset signals. In powerdown mode, the external clock signal is not loaded by the chip.  
6.11.8 DEFAULT RESET CONDITIONS  
The LPC47S45x has one source of hardware reset: an external reset via the PCI_RESET# pin. Refer to Table 55 for  
the effect of each type of reset on the internal registers.  
Table 55 Resets  
HARDWARE RESET  
DESCRIPTION  
(PCI_RESET#)  
KCLK  
Low  
Low  
Low  
Low  
N/A  
00H  
KDAT  
MCLK  
MDAT  
Host I/F Data Reg  
Host I/F Status Reg  
N/A: Not Applicable  
GATEA20 And Keyboard Reset  
The LPC47S45x provides two options for GateA20 and Keyboard Reset: 8042 Software Generated GateA20 and  
KRESET and Port 92 Fast GateA20 and KRESET.  
Port 92 Fast GATEA20 and Keyboard Reset  
Port 92 Register  
This port can only be read or written if Port 92 has been enabled via bit 2 of the KRST_GA20 Register (Logical  
Device 7, 0xF0) set to 1.  
This register is used to support the alternate reset (nALT_RST) and alternate A20 (ALT_A20) functions.  
NAME  
Port 92  
92h  
LOCATION  
DEFAULT  
VALUE  
24h  
ATTRIBUTE  
SIZE  
Read/Write  
8 bits  
PORT 92 REGISTER  
FUNCTION  
BIT  
7:6  
5
Reserved. Returns 00 when read  
Reserved. Returns a 1 when read  
Reserved. Returns a 0 when read  
Reserved. Returns a 0 when read  
Reserved. Returns a 1 when read  
4
3
2
1
ALT_A20 Signal control. Writing a 0 to this bit causes the ALT_A20 signal to be driven low. Writing a 1  
to this bit causes the ALT_A20 signal to be driven high.  
SMSC LPC47S45x  
Page 111 of 259  
Rev. 06-01-06  
DATASHEET  
 复制成功!