6.11 8042 Keyboard Controller Description
The LPC47S45x is a Super I/O and Universal Keyboard Controller that is designed for intelligent keyboard management
in desktop computer applications.
The Universal Keyboard Controller uses an 8042 microcontroller CPU core. This section concentrates on the
LPC47S45x enhancements to the 8042. For general information about the 8042, refer to the "Hardware Description of
the 8042" in the 8-Bit Embedded Controller Handbook.
8042A
LS05
P27
P10
KDAT
KCLK
MCLK
MDAT
P26
TST0
P23
TST1
P22
P11
Keyboard and Mouse Interface
KIRQ is the Keyboard IRQ
MIRQ is the Mouse IRQ
Port 21 is used to create a GATEA20 signal from the LPC47S45x.
6.11.1 KEYBOARD INTERFACE
The LPC47S45x LPC interface is functionally compatible with the 8042 style host interface. It consists of the D0-7 data
signals; the read and write signals and the Status register, Input Data register, and Output Data register. Table 52 shows
how the interface decodes the control signals. In addition to the above signals, the host interface includes keyboard and
mouse IRQs.
Table 52 − I/O Address Map
ADDRESS
COMMAND
Write
BLOCK
KDATA
KDATA
KDCTL
KDCTL
FUNCTION (NOTE 1)
Keyboard Data Write (C/D=0)
Keyboard Data Read
0x60
Read
0x64
Write
Keyboard Command Write (C/D=1)
Keyboard Status Read
Read
Note 1: These registers consist of three separate 8 bit registers. Status, Data/Command Write and Data Read.
Keyboard Data Write
This is an 8 bit write only register. When written, the C/D status bit of the status register is cleared to zero and the IBF
bit is set.
Keyboard Data Read
This is an 8 bit read only register. If enabled by "ENABLE FLAGS", when read, the KIRQ output is cleared and the OBF
flag in the status register is cleared. If not enabled, the KIRQ and/or AUXOBF1 must be cleared in software.
SMSC DS – LPC47S45x
Page 108 of 259
Rev. 07/09/2001
DATASHEET
SMSC [ SMSC CORPORATION ]
