Bit 7 – MIDI Receive Buffer Empty
Bit 7 MIDI Receive Buffer Empty indicates the read state of the MIDI Data port (Table 36). If the MRBE bit is ‘0’, MIDI
Read/Command Acknowledge data is available to the host. If the MRBE bit is ‘1’, MIDI Read/Command
Acknowledge data is NOT available to the host.
The MPU-401 Interrupt output is active ‘1’ when the MIDI Receive Buffer Empty bit is ‘0’. The MPU-401 Interrupt
output is inactive ‘0’ when the MIDI Receive Buffer Empty bit is ‘1’. See Section “Interrupt” for more information.
TABLE 36 - MIDI RECEIVE BUFFER EMPTY STATUS BIT
STATUS PORT
D7
0
DESCRIPTION
MIDI Read/Command Acknowledge data is
available to the host.
1
MIDI Read/Command Acknowledge data is
NOT available to the host.
Bit 6 – MIDI Transmit Busy
Bit 6 MIDI Transmit Busy indicates the send (write) state of the MIDI Data port and Command port (Table 37).
There are no interrupts associated with MIDI transmit (write) data.
TABLE 37 - MIDI TRANSMIT BUSY STATUS BIT
STATUS PORT DESCRIPTION
D6
0
The MPU-401 interface is ready to accept a
data/command byte from the host.
1
The MPU-401 interface is NOT ready to
accept a data/command byte from the host.
Bits[5:0]
RESERVED (Reserved bits cannot be written and return ‘0’ when read).
Command Port
The Command port is used to transfer MPU-401 commands to the Command Controller. The Command port is write-
only (Table 38). See Section “MPU-401 Command Controller” below.
TABLE 38 – MPU-401 COMMAND PORT
MPU-401 I/O BASE ADDRESS+1
D7
W
D6
W
D5
W
D4
W
D3
W
D2
W
D1
W
D0
W
DEFAULT
n/a
TYPE
NAME
COMMAND REGISTER
Interrupt
The MPU-401 IRQ is asserted (‘1’) when either MIDI receive data or a command acknowledge byte is available to the
host in the MIDI Data register (Figure 3). The IRQ is deasserted (‘0’) when the host reads the MIDI Data port.
NOTE: If, following a host read, data is still available in the Receive FIFO, the IRQ will remain asserted (‘1’).
The IRQ is enabled when the ‘Activate’ bit in the MPU-401 configuration registers logical device block is asserted ‘1’.
If the Activate bit is deasserted ‘0’, the MPU-401 IRQ cannot be asserted (see Section “MPU-401 Configuration
Registers”).
The MPU-401 IRQ is not affected by MIDI write data, transmit-related functions or Receiver Line Status interrupts.
The factory default Sound Blaster 16 MPU-401 IRQ is 5.
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