Table 39 - Parallel Port Connector
HOST
CONNECTOR
PIN NUMBER
STANDARD
nSTROBE
PD<0:7>
nACK
BUSY
PE
EPP
ECP
1
83
68-75
80
79
78
nWrite
nStrobe
2-9
10
11
12
PData<0:7>
Intr
PData<0:7>
nAck
Busy, PeriphAck(3)
PError,
nWait
(User Defined)
nAckReverse(3)
13
14
77
82
SLCT
nALF
(User Defined)
nDatastb
Select
nAutoFd,
HostAck(3)
15
16
17
81
66
67
nERROR
nINIT
(User Defined)
nRESET
nFault(1)
nPeriphRequest(3)
nInit(1)
nReverseRqst(3)
nSelectIn(1,3)
nSLCTIN
nAddrstrb
(1) = Compatible Mode
(3) = High Speed Mode
Note:
For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the
IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. This document is available
from Microsoft.
IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES
DATA PORT
ADDRESS OFFSET = 00H
The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by
RESET. During a WRITE operation, the Data Register latches the contents of the internal data bus. The contents of
this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation in SPP mode,
PD0 - PD7 ports are buffered (not latched) and output to the host CPU.
STATUS PORT
ADDRESS OFFSET = 01H
The Status Port is located at an offset of '01H' from the base address. The contents of this register are latched for the
duration of a read cycle. The bits of the Status Port are defined as follows:
BIT 0 TMOUT - TIME OUT
This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A logic O means
that no time out error has occurred; a logic 1 means that a time out error has been detected. This bit is cleared by a
RESET. If the TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode Register 2, 0xF1 in Logical Device 3 Configuration
Registers) is ‘0’, writing a one to this bit clears the TMOUT status bit. Writing a zero to this bit has no effect. If the
TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode Register 2, 0xF1 in Logical Device 3 Configuration Registers) is
‘1’, the TMOUT bit is cleared on the trailing edge of a read of the EPP Status Register.
BITS 1, 2 - are not implemented as register bits, during a read of the Printer Status Register these bits are a low level.
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