The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt whenever the Tx FIFO
is empty and the Tx interrupt is enabled, except in the following instance. Assume that the Tx FIFO is empty and the
CPU starts to load it. When the first byte enters the FIFO the Tx FIFO empty interrupt will transition from active to
inactive. Depending on the execution speed of the service routine software, the UART may be able to transfer this byte
from the FIFO to the shift register before the CPU loads another byte. If this happens, the Tx FIFO will be empty again
and typically the UART's interrupt line would transition to the active state. This could cause a system with an interrupt
control unit to record a Tx FIFO empty condition, even though the CPU is currently servicing that interrupt. Therefore,
after the first byte has been loaded into the FIFO the UART will wait one serial character transmission time
before issuing a new Tx FIFO empty interrupt. This one character Tx interrupt delay will remain active until at
least two bytes have the Tx FIFO empties after this condition, the Tx been loaded into the FIFO, concurrently.
When interrupt will be activated without a one character delay.
Rx support functions and operation are quite different from those described for the transmitter. The Rx FIFO receives
data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if Rx interrupts are
enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it holds 16 of them.
It will not accept any more data when it is full. Any more data entering the Rx shift register will set the Overrun Error flag.
Normally, the FIFO depth and the programmable trigger levels will give the CPU ample time to empty the Rx FIFO
before an overrun occurs.
One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data level in the FIFO.
This could occur when data at the end of the block contains fewer bytes than the trigger level. No interrupt would be
issued to the CPU and the data would remain in the UART. To prevent the software from having to check for this
situation the chip incorporates a timeout interrupt.
The timeout interrupt is activated when there is a least one byte in the Rx FIFO, and neither the CPU nor the Rx shift
register has accessed the Rx FIFO within 4 character times of the last byte. The timeout interrupt is cleared or reset
when the CPU reads the Rx FIFO or another character enters it.
These FIFO related features allow optimization of CPU/UART transactions and are especially useful given the higher
baud rate capability (256 kbaud).
INFRARED INTERFACE
The infrared interface provides a two-way wireless communications port using infrared as a transmission medium. Two
IR implementations have been provided for the second UART in this chip (logical device 5), IrDA and Amplitude Shift
Keyed IR. The IR transmission can use the standard UART2 TXD2 and RXD2 pins or optional IRTX2 and IRRX2 pins.
These can be selected through the configuration registers.
IrDA 1.0 allows serial communication at baud rates up to 115.2 kbps. Each word is sent serially beginning with a zero
value start bit. A zero is signaled by sending a single IR pulse at the beginning of the serial bit time. A one is signaled
by sending no IR pulse during the bit time. Please refer to the AC timing for the parameters of these pulses and the
IrDA waveform.
The Amplitude Shift Keyed IR allows asynchronous serial communication at baud rates up to 19.2K Baud. Each word is
sent serially beginning with a zero value start bit. A zero is signaled by sending a 500kHz waveform for the duration of
the serial bit time. A one is signaled by sending no transmission during the bit time. Please refer to the AC timing for the
parameters of the ASK-IR waveform.
If the Half Duplex option is chosen, there is a time-out when the direction of the transmission is changed. This time-out
starts at the last bit transferred during a transmission and blocks the receiver input until the timeout expires. If the
transmit buffer is loaded with more data before the time-out expires, the timer is restarted after the new byte is
transmitted. If data is loaded into the transmit buffer while a character is being received, the transmission will not start
until the time-out expires after the last receive bit has been received. If the start bit of another character is received
during this time-out, the timer is restarted after the new character is received. The IR half duplex time-out is
programmable via CRF2 in Logical Device 5. This register allows the time-out to be programmed to any value between 0
and 10msec in 100usec increments.
IR Transmit Pins
The following description pertains to the IRTX and IRTX2 pins of the LPC47M10x.
Page 66
SMSC [ SMSC CORPORATION ]
