Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
The SPI instructions supported by the LAN9313/LAN9313i are listed in Table 8.10. Unsupported
instructions are must not be used.
Table 8.10 Supported SPI Instructions
DESCRIPTION
INSTRUCTION
FORMAT
READ
0000 0011
Read register at the specified address.
Multiple reads maintain the same address.
READ_INC
READ_DEC
WRITE
0000 0111
0000 1011
0000 0010
0000 0110
0000 1010
Read register(s) starting at the specified address.
Multiple reads auto-increment address.
Read register(s) starting at the specified address.
Multiple reads auto-decrement address.
Write register at the specified address.
Multiple writes maintain the same address.
WRITE_INC
WRITE_DEC
Write register(s) starting at the specified address.
Multiple writes auto-increment address.
Write register(s) starting at the specified address.
Multiple writes auto-decrement address.
8.4.1
SPI Read Sequence
The SPI slave interface of the LAN9313/LAN9313i is selected for reads by first bringing nSCS low.
The SI pin should then driven with an 8-bit read instruction, followed by the 8-bit address. On the falling
clock edge which follows the rising edge of the last address bit, the SO output is driven starting with
the msb of the selected register. The remaining register bits are shifted out on subsequent falling clock
edges.
Multiple reads are performed by continuing the clock pulses while nSCS is low. Depending on the
instruction (as shown in Table 8.10), the internal address is incremented, decremented, or maintained.
Maintaining a fixed internal address is useful for register polling. For auto-incrementing instructions,
once the internal address reaches its maximum, it rolls over to 0. For auto-decrementing instructions,
once the internal address reaches 0, it rolls over to its maximum.
The nSCS input is brought high to conclude the cycle. The SO output pin is three-stated at this time.
Since data is read serially, register values are latched (registered) at the beginning of each 32-bit read
to prevent the host from reading an intermediate value. The latching occurs multiple times in a multiple
read sequence. In addition, any register that is affected by a read operation (e.g. a clear on read bit)
is not cleared until after all 32-bits are output. In the event that 32-bits are not read when the nSCS is
returned high, the read is considered invalid and the register is not affected. Multiple registers may be
cleared in a multiple read cycle, each one being cleared as it is read.
SPI reads from unused register addresses return as all zeros.
SMSC LAN9313/LAN9313i
119
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
