Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
LAN9313/LAN9313i, the master may either send data bytes to be written, or it may send another start
condition (to start the reading of data), or a stop condition. The latter two will terminate the current
write (without writing any data), but will have the affect of setting the internal register address which
will be used for subsequent reads.
If the read/write indication in the control byte is a 1 (indicating a read), the LAN9313/LAN9313i will
start sending data following the control byte acknowledgement.
Note: All registers are accessed as DWORDs. Appending two 0 bits to the address field will form the
register address. Addresses and data are transferred msb first. Data is transferred MSB first
(little endian).
Control Byte
Address Byte
S
A
6
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
S
A
0
A
C
K
A
C
K
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
S
0
*
Start or
Stop or
Data [31]
R/~W
Figure 8.3 I2C Slave Addressing
2
8.5.2
I C Slave Read Sequence
Following the device addressing, as detailed in Section 8.5.1, a register is read from the
LAN9313/LAN9313i when the master sends a start condition and control byte with the R/~W bit set.
Assuming the slave address in the control byte matches the LAN9313/LAN9313i address, the control
byte is acknowledged by the LAN9313/LAN9313i. Otherwise, the entire sequence is ignored until the
next start condition. Following the acknowledge, the LAN9313/LAN9313i sends 4 bytes of data. The
first 3 bytes are acknowledged by the master and on the fourth, the master sends a no-acknowledge
followed by the stop condition. The no-acknowledge informs the LAN9313/LAN9313i not to send the
next 4 bytes (as it would in the case of a multiple read). The internal register address is unchanged
following the single read.
Multiple reads are performed when the master sends an acknowledge on the fourth byte. The internal
address is incremented and the next register is shifted out. Once the internal address reaches its
maximum, it rolls over to 0. The multiple read is concluded when the master sends a no-acknowledge
followed by a stop condition. The no-acknowledge informs the LAN9313/LAN9313i not to send the next
4 bytes. The internal register address in incremented for each read including the final.
For both single and multiple reads, in the case that the master sends a no-acknowledge on any of the
first three bytes of the register, the LAN9313/LAN9313i will stop sending subsequent bytes. If the
master sends an unexpected start or stop condition, the LAN9313/LAN9313i will stop sending
immediately and will respond to the next sequence as needed.
Since data is read serially, register values are latched (registered) at the beginning of each 32-bit read
to prevent the host from reading an intermediate value. The latching occurs multiple times in a multiple
read sequence. In addition, any register that is affected by a read operation (e.g. a clear on read bit)
is not cleared until after all 32-bits are output. In the event that 32-bits are not read (master sends a
no-acknowledge on one of the first three bytes or a start or stop condition occurs unexpectedly), the
read is considered invalid and the register is not affected. Multiple registers may be cleared in a
2
multiple read cycle, each one being cleared as it is read. I C reads from unused register addresses
return all zeros.
Revision 1.2 (04-08-08)
122
SMSC LAN9313/LAN9313i
DATASHEET
SMSC [ SMSC CORPORATION ]
